controller port readiness (that should set just after PHY ready signal), reduce wait time from 10s to 1s before trying more aggressive reset method. This should improve system responsibility in some failure conditions. |
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.. | ||
siis.c | ||
siis.h |
controller port readiness (that should set just after PHY ready signal), reduce wait time from 10s to 1s before trying more aggressive reset method. This should improve system responsibility in some failure conditions. |
||
---|---|---|
.. | ||
siis.c | ||
siis.h |