144 lines
4.8 KiB
C
144 lines
4.8 KiB
C
/*-
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* Copyright (c) 1997, 1998, 1999, 2000
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* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Definitions for the CATC Netmate II USB to ethernet controller.
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*/
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/* Vendor specific control commands. */
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#define CUE_CMD_RESET 0xF4
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#define CUE_CMD_GET_MACADDR 0xF2
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#define CUE_CMD_WRITEREG 0xFA
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#define CUE_CMD_READREG 0xFB
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#define CUE_CMD_READSRAM 0xF1
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#define CUE_CMD_WRITESRAM 0xFC
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/* Internal registers. */
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#define CUE_TX_BUFCNT 0x20
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#define CUE_RX_BUFCNT 0x21
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#define CUE_ADVANCED_OPMODES 0x22
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#define CUE_TX_BUFPKTS 0x23
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#define CUE_RX_BUFPKTS 0x24
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#define CUE_RX_MAXCHAIN 0x25
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#define CUE_ETHCTL 0x60
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#define CUE_ETHSTS 0x61
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#define CUE_PAR5 0x62
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#define CUE_PAR4 0x63
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#define CUE_PAR3 0x64
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#define CUE_PAR2 0x65
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#define CUE_PAR1 0x66
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#define CUE_PAR0 0x67
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/* Error counters, all 16 bits wide. */
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#define CUE_TX_SINGLECOLL 0x69
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#define CUE_TX_MULTICOLL 0x6B
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#define CUE_TX_EXCESSCOLL 0x6D
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#define CUE_RX_FRAMEERR 0x6F
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#define CUE_LEDCTL 0x81
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/* Advenced operating mode register. */
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#define CUE_AOP_SRAMWAITS 0x03
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#define CUE_AOP_EMBED_RXLEN 0x08
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#define CUE_AOP_RXCOMBINE 0x10
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#define CUE_AOP_TXCOMBINE 0x20
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#define CUE_AOP_EVEN_PKT_READS 0x40
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#define CUE_AOP_LOOPBK 0x80
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/* Ethernet control register. */
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#define CUE_ETHCTL_RX_ON 0x01
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#define CUE_ETHCTL_LINK_POLARITY 0x02
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#define CUE_ETHCTL_LINK_FORCE_OK 0x04
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#define CUE_ETHCTL_MCAST_ON 0x08
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#define CUE_ETHCTL_PROMISC 0x10
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/* Ethernet status register. */
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#define CUE_ETHSTS_NO_CARRIER 0x01
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#define CUE_ETHSTS_LATECOLL 0x02
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#define CUE_ETHSTS_EXCESSCOLL 0x04
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#define CUE_ETHSTS_TXBUF_AVAIL 0x08
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#define CUE_ETHSTS_BAD_POLARITY 0x10
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#define CUE_ETHSTS_LINK_OK 0x20
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/* LED control register. */
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#define CUE_LEDCTL_BLINK_1X 0x00
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#define CUE_LEDCTL_BLINK_2X 0x01
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#define CUE_LEDCTL_BLINK_QUARTER_ON 0x02
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#define CUE_LEDCTL_BLINK_QUARTER_OFF 0x03
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#define CUE_LEDCTL_OFF 0x04
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#define CUE_LEDCTL_FOLLOW_LINK 0x08
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/*
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* Address in ASIC's internal SRAM where the multicast hash table lives.
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* The table is 64 bytes long, giving us a 512-bit table. We have to set
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* the bit that corresponds to the broadcast address in order to enable
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* reception of broadcast frames.
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*/
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#define CUE_MCAST_TABLE_ADDR 0xFA80
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#define CUE_MCAST_TABLE_LEN 64
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#define CUE_TIMEOUT 1000
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#define CUE_MIN_FRAMELEN 60
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#define CUE_RX_FRAMES 1
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#define CUE_TX_FRAMES 1
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#define CUE_CTL_READ 0x01
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#define CUE_CTL_WRITE 0x02
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#define CUE_CONFIG_IDX 0 /* config number 1 */
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#define CUE_IFACE_IDX 0
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/* The interrupt endpoint is currently unused by the KLSI part. */
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enum {
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CUE_BULK_DT_WR,
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CUE_BULK_DT_RD,
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CUE_BULK_CS_WR,
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CUE_BULK_CS_RD,
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CUE_N_TRANSFER = 4,
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};
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struct cue_softc {
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struct ifnet *sc_ifp;
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struct usb2_config_td sc_config_td;
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struct usb2_callout sc_watchdog;
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struct mtx sc_mtx;
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device_t sc_dev;
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struct usb2_device *sc_udev;
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struct usb2_xfer *sc_xfer[CUE_N_TRANSFER];
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uint32_t sc_unit;
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uint16_t sc_flags;
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#define CUE_FLAG_READ_STALL 0x0010 /* wait for clearing of stall */
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#define CUE_FLAG_WRITE_STALL 0x0020 /* wait for clearing of stall */
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#define CUE_FLAG_LL_READY 0x0040 /* Lower Layer Ready */
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#define CUE_FLAG_HL_READY 0x0080 /* Higher Layer Ready */
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#define CUE_FLAG_INTR_STALL 0x0100 /* wait for clearing of stall */
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};
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