188 lines
6.9 KiB
C
188 lines
6.9 KiB
C
/* $FreeBSD$ */
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/* $NecBSD: ncr53c500reg.h,v 1.5.14.1 2001/06/08 06:27:44 honda Exp $ */
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/* $NetBSD$ */
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/*-
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* [NetBSD for NEC PC-98 series]
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* Copyright (c) 1995, 1996, 1997, 1998
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* NetBSD/pc98 porting staff. All rights reserved.
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* Copyright (c) 1995, 1996, 1997, 1998
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* Naofumi HONDA. All rights reserved.
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* Copyright (c) 1995, 1996, 1997, 1998
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* Kouichi Matsuda. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NCR53C500REG_H_
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#define _NCR53C500REG_H_
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/* Control Register Set 0 */
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#define NCVIOSZ 0x10
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#define cr0_tclsb 0x00 /* RW - Transfer Count Low */
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#define cr0_tcmsb 0x01 /* RW - Transfer Count Mid */
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#define cr0_sfifo 0x02 /* RW - FIFO data */
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#define cr0_cmd 0x03 /* RW - Command (2 deep) */
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#define cr0_stat 0x04 /* RO - Status */
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#define cr0_dstid 0x04 /* WO - Select/Reselect Bus ID */
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#define cr0_istat 0x05 /* RO - Interrupt */
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#define cr0_srtout 0x05 /* WO - Select/Reselect Timeout */
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#define cr0_seq 0x06 /* RO - Sequence Step */
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#define cr0_period 0x06 /* WO - Synch Transfer Period */
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#define cr0_sffl 0x07 /* RO - FIFO FLags */
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#define cr0_offs 0x07 /* WO - Synch Ofset */
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#define cr0_cfg1 0x08 /* RW - Configuration #1 */
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#define cr0_clk 0x09 /* WO - Clock Conversion Factor */
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#define cr0_tst 0x0a /* WO - Test (Chip Test Only) */
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#define cr0_cfg2 0x0b /* RW - Configuration #2 */
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#define cr0_cfg3 0x0c /* RW - Configuration #3 */
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#define cr0_cfg4 0x0d /* RW - Configuration #4 */
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#define cr0_tchsb 0x0e /* RW - Transfer Count High */
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#define cr0_fifo_bottom 0x0f /* WO - FIFO bottom */
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/* Control Register Set 1 */
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#define cr1_jumper 0x00 /* RW - Jumper Sense Port */
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#define cr1_sram_ptr 0x01 /* RW - SRAM Address Pointer */
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#define cr1_sram_data 0x02 /* RW - SRAM Data */
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#define cr1_fdata 0x04 /* RW - PIO FIFO */
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#define cr1_fstat 0x08 /* RW - PIO Status */
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#define cr1_atacmd 0x09 /* RW - ATA Command/Status */
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#define cr1_ataerr 0x0a /* RW - ATA Features/Error */
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#define cr1_pflag 0x0b /* RW - PIO Flag Interrupt Enable */
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#define cr1_cfg5 0x0d /* RW - Configuration #5 */
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#define cr1_sig 0x0e /* RO - Signature */
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#define cr1_cfg6 0x0f /* RW - Configuration #6 */
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/* atacmd (MPS110 ONLY) */
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#define ATACMD_POWDOWN 0x2d
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#define ATACMD_ENGAGE 0x24
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/* cr0_sffl regster */
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#define CR0_SFFLR_BMASK 0x1f /* scsi fifo byte mask */
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/* cfg4 */
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#define C4_ANE 0x04
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/* cfg2 */
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#define C2_SCSI2 0x08 /* SCSI-2 Enable */
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#define C2_FE 0x40 /* Features Enable */
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/* cfg1 */
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#define C1_SLOW 0x80 /* Slow Cable Mode */
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#define C1_SRR 0x40 /* SCSI Reset Rep Int Dis */
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#define C1_PARENB 0x10 /* Enable Parity Check */
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/* clk factor */
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#define CLK_40M_F 0x00
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#define CLK_25M_F 0x05
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#define CLK_30M_F 0x06
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#define CLK_35M_F 0x07
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/* interrupt status register */
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#define INTR_SBR 0x80 /* SCSI Bus Reset */
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#define INTR_ILL 0x40 /* Illegal Command */
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#define INTR_DIS 0x20 /* Disconnect */
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#define INTR_BS 0x10 /* Bus Service */
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#define INTR_FC 0x08 /* Function Complete */
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#define INTR_RESEL 0x04 /* Reselected */
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#define INTR_SELATN 0x02 /* Select with ATN */
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#define INTR_SEL 0x01 /* Selected */
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#define INTR_RESELECT (INTR_RESEL | INTR_FC)
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/* status register */
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#define STAT_INT 0x80 /* Interrupt */
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#define STAT_GE 0x40 /* Gross Error */
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#define STAT_PE 0x20 /* Parity Error */
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#define STAT_TC 0x10 /* Terminal Count */
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/* phase bits */
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#define IOI 0x01
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#define CDI 0x02
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#define MSGI 0x04
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/* Information transfer phases */
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#define DATA_OUT_PHASE (0)
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#define DATA_IN_PHASE (IOI)
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#define COMMAND_PHASE (CDI)
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#define STATUS_PHASE (CDI|IOI)
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#define MESSAGE_OUT_PHASE (MSGI|CDI)
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#define MESSAGE_IN_PHASE (MSGI|CDI|IOI)
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#define PHASE_MASK (MSGI|CDI|IOI)
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/* fifo status register */
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#define FIFO_SMASK 0x1e
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#define FIFO_E 0x10 /* fifo empty */
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#define FIFO_B 0x00 /* there exists any */
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#define FIFO_1 0x08 /* 1/3 <= bytes < 2/3 */
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#define FIFO_2 0x04 /* 2/3 <= bytes < full */
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#define FIFO_F 0x02 /* full */
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#define FIFO_EN 0x01 /* fifo direction */
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#define FIFO_BRK 0x40 /* phase miss */
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#define FIFO_F_SZ 128
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#define FIFO_1_SZ 44
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#define FIFO_2_SZ 84
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/* pflags */
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#define PFR_WRITE 0x01
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/* Commands */
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#define CMD_DMA 0x80 /* DMA Bit */
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#define CMD_NOP 0x00 /* No Operation */
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#define CMD_FLUSH 0x01 /* Flush FIFO */
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#define CMD_RSTCHIP 0x02 /* Reset Chip */
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#define CMD_RSTSCSI 0x03 /* Reset SCSI Bus */
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#define CMD_RESEL 0x40 /* Reselect Sequence */
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#define CMD_SELNATN 0x41 /* Select without ATN */
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#define CMD_SELATN 0x42 /* Select with ATN */
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#define CMD_SELATNS 0x43 /* Select with ATN & Stop */
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#define CMD_ENSEL 0x44 /* Enable (Re)Selection */
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#define CMD_DISSEL 0x45 /* Disable (Re)Selection */
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#define CMD_SELATN3 0x46 /* Select with ATN3 */
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#define CMD_RESEL3 0x47 /* Reselect3 Sequence */
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#define CMD_SNDMSG 0x20 /* Send Message */
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#define CMD_SNDSTAT 0x21 /* Send Status */
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#define CMD_SNDDATA 0x22 /* Send Data */
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#define CMD_DISCSEQ 0x23 /* Disconnect Sequence */
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#define CMD_TERMSEQ 0x24 /* Terminate Sequence */
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#define CMD_TCCS 0x25 /* Target Command Comp Seq */
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#define CMD_DISC 0x27 /* Disconnect */
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#define CMD_RECMSG 0x28 /* Receive Message */
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#define CMD_RECCMD 0x29 /* Receive Command */
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#define CMD_RECDATA 0x2a /* Receive Data */
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#define CMD_RECCSEQ 0x2b /* Receive Command Sequence */
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#define CMD_ABORT 0x04 /* Target Abort DMA */
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#define CMD_TRANS 0x10 /* Transfer Information */
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#define CMD_ICCS 0x11 /* Initiator Cmd Comp Seq */
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#define CMD_MSGOK 0x12 /* Message Accepted */
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#define CMD_TRPAD 0x18 /* Transfer Pad */
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#define CMD_SETATN 0x1a /* Set ATN */
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#define CMD_RSTATN 0x1b /* Reset ATN */
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/* Default timeout */
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#define SEL_TOUT 0xa3
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#endif /* !_NCR53C500REG_H_ */
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