702818d200
DBCR0, according to the Freescale EREF, is guaranteed to be updated, and changes take effect, after an isync plus change of MSR[DE] from 0 to 1. Otherwise it's guaranteed to be updated "eventually". Use the expected synchronization sequence to write it for resetting. This prevents "Reset failed" from being printed immediately before the CPU resets. MFC after: 2 weeks |
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aim | ||
booke | ||
conf | ||
cpufreq | ||
fpu | ||
include | ||
mambo | ||
mikrotik | ||
mpc85xx | ||
ofw | ||
powermac | ||
powernv | ||
powerpc | ||
ps3 | ||
pseries | ||
psim |