0aeed3e993
Freescale's QorIQ line includes a new ethernet controller, based on their Datapath Acceleration Architecture (DPAA). This uses a combination of a Frame manager, Buffer manager, and Queue manager to improve performance across all interfaces by being able to pass data directly between hardware acceleration interfaces. As part of this import, Freescale's Netcomm Software (ncsw) driver is imported. This was an attempt by Freescale to create an OS-agnostic sub-driver for managing the hardware, using shims to interface to the OS-specific APIs. This work was abandoned, and Freescale's primary work is in the Linux driver (dual BSD/GPL license). Hence, this was imported directly to sys/contrib, rather than going through the vendor area. Going forward, FreeBSD-specific changes may be made to the ncsw code, diverging from the upstream in potentially incompatible ways. An alternative could be to import the Linux driver itself, using the linuxKPI layer, as that would maintain parity with the vendor-maintained driver. However, the Linux driver has not been evaluated for reliability yet, and may have issues with the import, whereas the ncsw-based driver in this commit was completed by Semihalf 4 years ago, and is very stable. Other SoC modules based on DPAA, which could be added in the future: * Security and Encryption engine (SEC4.x, SEC5.x) * RAID engine Additional work to be done: * Implement polling mode * Test vlan support * Add support for the Pattern Matching Engine, which can do regular expression matching on packets. This driver has been tested on the P5020 QorIQ SoC. Others listed in the dtsec(4) manual page are expected to work as the same DPAA engine is included in all. Obtained from: Semihalf Relnotes: Yes Sponsored by: Alex Perez/Inertial Computing
122 lines
4.4 KiB
C
122 lines
4.4 KiB
C
/* Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "error_ext.h"
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#include "std_ext.h"
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#include "fm_mac.h"
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#include "tgec.h"
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#include "xx_ext.h"
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/*****************************************************************************/
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t_Error TGEC_MII_WritePhyReg(t_Handle h_Tgec,
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uint8_t phyAddr,
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uint8_t reg,
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uint16_t data)
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{
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t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
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t_TgecMiiAccessMemMap *p_MiiAccess;
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SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
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SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
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p_MiiAccess = p_Tgec->p_MiiMemMap;
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while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
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XX_UDelay (1);
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WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
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WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
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CORE_MemoryBarrier();
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while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
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XX_UDelay (1);
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WRITE_UINT32(p_MiiAccess->mdio_data, data);
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CORE_MemoryBarrier();
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while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
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XX_UDelay (1);
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return E_OK;
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}
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/*****************************************************************************/
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t_Error TGEC_MII_ReadPhyReg(t_Handle h_Tgec,
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uint8_t phyAddr,
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uint8_t reg,
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uint16_t *p_Data)
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{
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t_Tgec *p_Tgec = (t_Tgec *)h_Tgec;
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t_TgecMiiAccessMemMap *p_MiiAccess;
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uint32_t cfg_status;
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SANITY_CHECK_RETURN_ERROR(p_Tgec, E_INVALID_HANDLE);
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SANITY_CHECK_RETURN_ERROR(p_Tgec->p_MiiMemMap, E_INVALID_HANDLE);
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p_MiiAccess = p_Tgec->p_MiiMemMap;
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while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
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XX_UDelay (1);
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WRITE_UINT32(p_MiiAccess->mdio_command, phyAddr);
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WRITE_UINT32(p_MiiAccess->mdio_regaddr, reg);
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CORE_MemoryBarrier();
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while ((GET_UINT32(p_MiiAccess->mdio_cfg_status)) & MIIMIND_BUSY)
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XX_UDelay (1);
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WRITE_UINT32(p_MiiAccess->mdio_command, (uint32_t)(phyAddr | MIIMCOM_READ_CYCLE));
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CORE_MemoryBarrier();
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while ((GET_UINT32(p_MiiAccess->mdio_data)) & MIIDATA_BUSY)
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XX_UDelay (1);
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*p_Data = (uint16_t)GET_UINT32(p_MiiAccess->mdio_data);
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cfg_status = GET_UINT32(p_MiiAccess->mdio_cfg_status);
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if (cfg_status & MIIMIND_READ_ERROR)
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RETURN_ERROR(MINOR, E_INVALID_VALUE,
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("Read Error: phyAddr 0x%x, dev 0x%x, reg 0x%x, cfg_status 0x%x",
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((phyAddr & 0xe0)>>5), (phyAddr & 0x1f), reg, cfg_status));
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return E_OK;
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}
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