231 lines
6.3 KiB
C
231 lines
6.3 KiB
C
/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner clock gates
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_subr.h>
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#include <dev/extres/clk/clk_gate.h>
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#define GATE_OFFSET(index) ((index / 32) * 4)
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#define GATE_SHIFT(index) (index % 32)
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10-dram-gates-clk",
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(uintptr_t)"Allwinner DRAM Clock Gates" },
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{ "allwinner,sun4i-a10-ahb-gates-clk",
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(uintptr_t)"Allwinner AHB Clock Gates" },
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{ "allwinner,sun4i-a10-apb0-gates-clk",
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(uintptr_t)"Allwinner APB0 Clock Gates" },
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{ "allwinner,sun4i-a10-apb1-gates-clk",
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(uintptr_t)"Allwinner APB1 Clock Gates" },
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{ "allwinner,sun5i-a13-ahb-gates-clk",
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(uintptr_t)"Allwinner AHB Clock Gates" },
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{ "allwinner,sun5i-a13-apb0-gates-clk",
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(uintptr_t)"Allwinner APB0 Clock Gates" },
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{ "allwinner,sun5i-a13-apb1-gates-clk",
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(uintptr_t)"Allwinner APB1 Clock Gates" },
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{ "allwinner,sun7i-a20-ahb-gates-clk",
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(uintptr_t)"Allwinner AHB Clock Gates" },
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{ "allwinner,sun7i-a20-apb0-gates-clk",
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(uintptr_t)"Allwinner APB0 Clock Gates" },
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{ "allwinner,sun7i-a20-apb1-gates-clk",
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(uintptr_t)"Allwinner APB1 Clock Gates" },
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{ "allwinner,sun6i-a31-ahb1-gates-clk",
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(uintptr_t)"Allwinner AHB1 Clock Gates" },
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{ "allwinner,sun6i-a31-apb0-gates-clk",
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(uintptr_t)"Allwinner APB0 Clock Gates" },
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{ "allwinner,sun6i-a31-apb1-gates-clk",
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(uintptr_t)"Allwinner APB1 Clock Gates" },
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{ "allwinner,sun6i-a31-apb2-gates-clk",
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(uintptr_t)"Allwinner APB2 Clock Gates" },
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{ "allwinner,sun8i-a83t-bus-gates-clk",
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(uintptr_t)"Allwinner Bus Clock Gates" },
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{ "allwinner,sun8i-a83t-apb0-gates-clk",
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(uintptr_t)"Allwinner APB0 Clock Gates" },
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{ "allwinner,sun8i-h3-bus-gates-clk",
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(uintptr_t)"Allwinner Bus Clock Gates" },
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{ "allwinner,sun8i-h3-apb0-gates-clk",
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(uintptr_t)"Allwinner APB0 Clock Gates" },
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{ "allwinner,sun9i-a80-apbs-gates-clk",
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(uintptr_t)"Allwinner APBS Clock Gates" },
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{ "allwinner,sunxi-multi-bus-gates-clk",
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(uintptr_t)"Allwinner Multi Bus Clock Gates" },
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{ NULL, 0 }
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};
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static int
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aw_gate_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom,
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const char *pclkname, const char *clkname, int index)
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{
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const char *parent_names[1] = { pclkname };
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struct clk_gate_def def;
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memset(&def, 0, sizeof(def));
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def.clkdef.id = index;
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def.clkdef.name = clkname;
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def.clkdef.parent_names = parent_names;
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def.clkdef.parent_cnt = 1;
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def.offset = paddr + GATE_OFFSET(index);
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def.shift = GATE_SHIFT(index);
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def.mask = 1;
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def.on_value = 1;
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def.off_value = 0;
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return (clknode_gate_register(clkdom, &def));
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}
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static int
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aw_gate_add(device_t dev, struct clkdom *clkdom, phandle_t node,
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bus_addr_t paddr)
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{
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const char **names;
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uint32_t *indices;
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clk_t clk_parent;
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int index, nout, error;
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indices = NULL;
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nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
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if (nout == 0) {
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device_printf(dev, "no clock outputs found\n");
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return (ENOENT);
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}
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if (indices == NULL) {
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device_printf(dev, "no clock-indices property\n");
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return (ENXIO);
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}
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error = clk_get_by_ofw_index(dev, node, 0, &clk_parent);
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if (error != 0) {
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device_printf(dev, "cannot parse clock parent\n");
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return (ENXIO);
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}
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for (index = 0; index < nout; index++) {
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error = aw_gate_create(dev, paddr, clkdom,
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clk_get_name(clk_parent), names[index], indices[index]);
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if (error)
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return (error);
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}
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return (0);
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}
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static int
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aw_gate_probe(device_t dev)
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{
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const char *d;
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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d = (const char *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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if (d == NULL)
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return (ENXIO);
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device_set_desc(dev, d);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aw_gate_attach(device_t dev)
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{
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struct clkdom *clkdom;
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bus_addr_t paddr;
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bus_size_t psize;
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phandle_t node, child;
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node = ofw_bus_get_node(dev);
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if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
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device_printf(dev, "cannot parse 'reg' property\n");
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return (ENXIO);
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}
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clkdom = clkdom_create(dev);
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if (ofw_bus_is_compatible(dev, "allwinner,sunxi-multi-bus-gates-clk")) {
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for (child = OF_child(node); child > 0; child = OF_peer(child))
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aw_gate_add(dev, clkdom, child, paddr);
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} else
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aw_gate_add(dev, clkdom, node, paddr);
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if (clkdom_finit(clkdom) != 0) {
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device_printf(dev, "cannot finalize clkdom initialization\n");
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return (ENXIO);
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}
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if (bootverbose)
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clkdom_dump(clkdom);
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return (0);
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}
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static device_method_t aw_gate_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, aw_gate_probe),
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DEVMETHOD(device_attach, aw_gate_attach),
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DEVMETHOD_END
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};
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static driver_t aw_gate_driver = {
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"aw_gate",
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aw_gate_methods,
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0
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};
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static devclass_t aw_gate_devclass;
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EARLY_DRIVER_MODULE(aw_gate, simplebus, aw_gate_driver,
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aw_gate_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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