8cc6cc81dd
Copy sys/dev/rmi to sys/mips/rmi/dev [sic]. For devices that are on only one SoC, or family of SoC, we place them under sys/<vendor>/dev. I'll fix the build problems this causes as best I can since rmi kernel require external toolchains due to lack of support for rmi op-codes in the ancient binutils we have in the tree.
128 lines
3.9 KiB
C
128 lines
3.9 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD */
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/* MDIO Low level Access routines */
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/* All Phy's accessed from GMAC0 base */
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#ifndef _XGMAC_MDIO_H_
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#define _XGMAC_MDIO_H_
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static inline int
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xmdio_read(volatile unsigned int *_mmio,
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uint32_t phy_addr, uint32_t address);
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static inline void
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xmdio_write(volatile unsigned int *_mmio,
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uint32_t phy_addr, uint32_t address, uint32_t data);
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static inline void
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xmdio_address(volatile unsigned int *_mmio,
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uint32_t phy_addr, uint32_t dev_ad, uint32_t address);
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static inline void
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xmdio_address(volatile unsigned int *_mmio,
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uint32_t phy_addr, uint32_t dev_ad, uint32_t address)
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{
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uint32_t st_field = 0x0;
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uint32_t op_type = 0x0; /* address operation */
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uint32_t ta_field = 0x2;/* ta field */
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_mmio[0x11] = ((st_field & 0x3) << 30) |
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((op_type & 0x3) << 28) |
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((phy_addr & 0x1F) << 23) |
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((dev_ad & 0x1F) << 18) |
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((ta_field & 0x3) << 16) |
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((address & 0xffff) << 0);
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_mmio[0x10] = (0x0 << 3) | 0x5;
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_mmio[0x10] = (0x1 << 3) | 0x5;
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_mmio[0x10] = (0x0 << 3) | 0x5;
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/* wait for dev_ad cycle to complete */
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while (_mmio[0x14] & 0x1) {
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};
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}
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/* function prototypes */
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static inline int
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xmdio_read(volatile unsigned int *_mmio,
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uint32_t phy_addr, uint32_t address)
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{
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uint32_t st_field = 0x0;
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uint32_t op_type = 0x3; /* read operation */
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uint32_t ta_field = 0x2;/* ta field */
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uint32_t data = 0;
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xmdio_address(_mmio, phy_addr, 5, address);
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_mmio[0x11] = ((st_field & 0x3) << 30) |
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((op_type & 0x3) << 28) |
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((phy_addr & 0x1F) << 23) |
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((5 & 0x1F) << 18) |
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((ta_field & 0x3) << 16) |
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((data & 0xffff) << 0);
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_mmio[0x10] = (0x0 << 3) | 0x5;
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_mmio[0x10] = (0x1 << 3) | 0x5;
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_mmio[0x10] = (0x0 << 3) | 0x5;
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/* wait for write cycle to complete */
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while (_mmio[0x14] & 0x1) {
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};
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data = _mmio[0x11] & 0xffff;
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return (data);
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}
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static inline void
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xmdio_write(volatile unsigned int *_mmio,
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uint32_t phy_addr, uint32_t address, uint32_t data)
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{
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uint32_t st_field = 0x0;
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uint32_t op_type = 0x1; /* write operation */
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uint32_t ta_field = 0x2;/* ta field */
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xmdio_address(_mmio, phy_addr, 5, address);
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_mmio[0x11] = ((st_field & 0x3) << 30) |
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((op_type & 0x3) << 28) |
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((phy_addr & 0x1F) << 23) |
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((5 & 0x1F) << 18) |
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((ta_field & 0x3) << 16) |
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((data & 0xffff) << 0);
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_mmio[0x10] = (0x0 << 3) | 0x5;
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_mmio[0x10] = (0x1 << 3) | 0x5;
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_mmio[0x10] = (0x0 << 3) | 0x5;
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/* wait for write cycle to complete */
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while (_mmio[0x14] & 0x1) {
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};
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}
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#endif
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