421 lines
9.2 KiB
C
421 lines
9.2 KiB
C
/*-
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* Copyright (c) 2000 Andrew Gallatin
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <sys/malloc.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <alpha/isa/isavar.h>
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#include <alpha/pci/irongatereg.h>
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#include <alpha/pci/irongatevar.h>
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#include <alpha/pci/pcibus.h>
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#include <machine/bwx.h>
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#include <machine/intr.h>
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#include <machine/intrcnt.h>
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#include <machine/cpuconf.h>
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#include <machine/rpb.h>
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#include <machine/resource.h>
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#include <machine/sgmap.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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static devclass_t irongate_devclass;
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static device_t irongate0; /* XXX only one for now */
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struct irongate_softc {
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int junk; /* no softc */
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};
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#define IRONGATE_SOFTC(dev) (struct irongate_softc*) device_get_softc(dev)
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static alpha_chipset_inb_t irongate_inb;
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static alpha_chipset_inw_t irongate_inw;
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static alpha_chipset_inl_t irongate_inl;
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static alpha_chipset_outb_t irongate_outb;
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static alpha_chipset_outw_t irongate_outw;
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static alpha_chipset_outl_t irongate_outl;
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static alpha_chipset_readb_t irongate_readb;
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static alpha_chipset_readw_t irongate_readw;
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static alpha_chipset_readl_t irongate_readl;
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static alpha_chipset_writeb_t irongate_writeb;
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static alpha_chipset_writew_t irongate_writew;
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static alpha_chipset_writel_t irongate_writel;
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static alpha_chipset_maxdevs_t irongate_maxdevs;
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static alpha_chipset_cfgreadb_t irongate_cfgreadb;
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static alpha_chipset_cfgreadw_t irongate_cfgreadw;
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static alpha_chipset_cfgreadl_t irongate_cfgreadl;
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static alpha_chipset_cfgwriteb_t irongate_cfgwriteb;
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static alpha_chipset_cfgwritew_t irongate_cfgwritew;
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static alpha_chipset_cfgwritel_t irongate_cfgwritel;
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static alpha_chipset_addrcvt_t irongate_cvt_dense, irongate_cvt_bwx;
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static alpha_chipset_read_hae_t irongate_read_hae;
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static alpha_chipset_write_hae_t irongate_write_hae;
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static alpha_chipset_t irongate_chipset = {
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irongate_inb,
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irongate_inw,
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irongate_inl,
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irongate_outb,
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irongate_outw,
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irongate_outl,
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irongate_readb,
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irongate_readw,
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irongate_readl,
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irongate_writeb,
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irongate_writew,
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irongate_writel,
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irongate_maxdevs,
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irongate_cfgreadb,
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irongate_cfgreadw,
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irongate_cfgreadl,
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irongate_cfgwriteb,
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irongate_cfgwritew,
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irongate_cfgwritel,
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irongate_cvt_dense,
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irongate_cvt_bwx,
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irongate_read_hae,
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irongate_write_hae,
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};
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static u_int8_t
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irongate_inb(u_int32_t port)
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{
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alpha_mb();
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return ldbu(KV(IRONGATE_IO + port));
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}
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static u_int16_t
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irongate_inw(u_int32_t port)
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{
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alpha_mb();
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return ldwu(KV(IRONGATE_IO + port));
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}
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static u_int32_t
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irongate_inl(u_int32_t port)
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{
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alpha_mb();
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return ldl(KV(IRONGATE_IO + port));
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}
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static void
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irongate_outb(u_int32_t port, u_int8_t data)
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{
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stb(KV(IRONGATE_IO + port), data);
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alpha_mb();
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}
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static void
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irongate_outw(u_int32_t port, u_int16_t data)
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{
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stw(KV(IRONGATE_IO + port), data);
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alpha_mb();
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}
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static void
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irongate_outl(u_int32_t port, u_int32_t data)
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{
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stl(KV(IRONGATE_IO + port), data);
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alpha_mb();
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}
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static u_int8_t
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irongate_readb(u_int32_t pa)
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{
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alpha_mb();
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return ldbu(KV(IRONGATE_MEM + pa));
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}
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static u_int16_t
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irongate_readw(u_int32_t pa)
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{
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alpha_mb();
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return ldwu(KV(IRONGATE_MEM + pa));
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}
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static u_int32_t
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irongate_readl(u_int32_t pa)
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{
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alpha_mb();
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return ldl(KV(IRONGATE_MEM + pa));
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}
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static void
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irongate_writeb(u_int32_t pa, u_int8_t data)
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{
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stb(KV(IRONGATE_MEM + pa), data);
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alpha_mb();
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}
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static void
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irongate_writew(u_int32_t pa, u_int16_t data)
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{
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stw(KV(IRONGATE_MEM + pa), data);
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alpha_mb();
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}
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static void
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irongate_writel(u_int32_t pa, u_int32_t data)
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{
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stl(KV(IRONGATE_MEM + pa), data);
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alpha_mb();
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}
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static int
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irongate_maxdevs(u_int b)
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{
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return 12; /* XXX */
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}
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static void
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irongate_clear_abort(void)
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{
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alpha_mb();
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alpha_pal_draina();
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}
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static int
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irongate_check_abort(void)
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{
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alpha_pal_draina();
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alpha_mb();
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return 0;
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}
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#define IRONGATE_CFGADDR(b, s, f, r) \
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KV(IRONGATE_CONF | ((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
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#define CFGREAD(h, b, s, f, r, op, width, type) \
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vm_offset_t va; \
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type data; \
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va = IRONGATE_CFGADDR(b, s, f, r); \
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irongate_clear_abort(); \
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if (badaddr((caddr_t)va, width)) { \
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irongate_check_abort(); \
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return ~0; \
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} \
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data = ##op##(va); \
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if (irongate_check_abort()) \
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return ~0; \
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return data;
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#define CFWRITE(h, b, s, f, r, data, op, width) \
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vm_offset_t va; \
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va = IRONGATE_CFGADDR(b, s, f, r); \
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irongate_clear_abort(); \
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if (badaddr((caddr_t)va, width)) \
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return; \
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##op##(va, data); \
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irongate_check_abort();
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static u_int8_t
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irongate_cfgreadb(u_int h, u_int b, u_int s, u_int f, u_int r)
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{
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CFGREAD(h, b, s, f, r, ldbu, 1, u_int8_t)
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}
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static u_int16_t
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irongate_cfgreadw(u_int h, u_int b, u_int s, u_int f, u_int r)
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{
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CFGREAD(h, b, s, f, r, ldwu, 2, u_int16_t)
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}
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static u_int32_t
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irongate_cfgreadl(u_int h, u_int b, u_int s, u_int f, u_int r)
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{
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CFGREAD(h, b, s, f, r, ldl, 4, u_int32_t)
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}
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static void
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irongate_cfgwriteb(u_int h, u_int b, u_int s, u_int f, u_int r, u_int8_t data)
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{
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CFWRITE(h, b, s, f, r, data, stb, 1)
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}
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static void
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irongate_cfgwritew(u_int h, u_int b, u_int s, u_int f, u_int r, u_int16_t data)
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{
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CFWRITE(h, b, s, f, r, data, stw, 2)
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}
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static void
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irongate_cfgwritel(u_int h, u_int b, u_int s, u_int f, u_int r, u_int32_t data)
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{
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CFWRITE(h, b, s, f, r, data, stl, 4)
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}
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vm_offset_t
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irongate_cvt_bwx(vm_offset_t addr)
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{
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addr &= 0xffffffffUL;
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return (KV(addr | IRONGATE_MEM));
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}
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vm_offset_t
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irongate_cvt_dense(vm_offset_t addr)
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{
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return irongate_cvt_bwx(addr);
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}
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/*
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* There doesn't appear to be an hae on this platform
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*/
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static u_int64_t
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irongate_read_hae(void)
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{
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return 0;
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}
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static void
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irongate_write_hae(u_int64_t hae)
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{
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}
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static int irongate_probe(device_t dev);
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static int irongate_attach(device_t dev);
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static device_method_t irongate_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, irongate_probe),
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DEVMETHOD(device_attach, irongate_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
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DEVMETHOD(bus_release_resource, pci_release_resource),
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DEVMETHOD(bus_activate_resource, pci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
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DEVMETHOD(bus_setup_intr, isa_setup_intr),
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DEVMETHOD(bus_teardown_intr, isa_teardown_intr),
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{ 0, 0 }
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};
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static driver_t irongate_driver = {
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"irongate",
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irongate_methods,
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sizeof(struct irongate_softc),
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};
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void
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irongate_init()
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{
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static int initted = 0;
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if (initted) return;
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initted = 1;
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chipset = irongate_chipset;
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alpha_XXX_dmamap_or = 0UL;
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if (platform.pci_intr_init)
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platform.pci_intr_init();
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}
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static int
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irongate_probe(device_t dev)
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{
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if (irongate0)
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return ENXIO;
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irongate0 = dev;
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device_set_desc(dev, "AMD 751 Core Logic chipset");
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pci_init_resources();
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isa_init_intr();
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device_add_child(dev, "pcib", 0);
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return 0;
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}
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static int
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irongate_attach(device_t dev)
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{
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u_int8_t value;
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pcicfgregs southbridge;
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irongate_init();
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if (!platform.iointr) /* XXX */
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set_iointr(alpha_dispatch_intr);
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snprintf(chipset_type, sizeof(chipset_type), "irongate");
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chipset_bwx = 1;
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chipset_ports = IRONGATE_IO;
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chipset_memory = IRONGATE_MEM;
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chipset_dense = IRONGATE_MEM;
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/* no s/g support in this chipset, must use bounce-buffers */
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chipset.sgmap = NULL;
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/*
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* XXX -- The SRM console doesn't properly initialize
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* the AcerLabs M1533C southbridge. We must turn off 32-bit
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* DMA support.
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*/
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southbridge.hose = 0;
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southbridge.bus = 0;
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southbridge.slot = 7;
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southbridge.func = 0;
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if ((0x153310b9 == pci_cfgread(&southbridge, PCIR_DEVVENDOR, 4))) {
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value = (u_int8_t)pci_cfgread(&southbridge, 0x42, 1);
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value &= ~0x40;
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pci_cfgwrite(&southbridge, 0x42, 0, 1);
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}
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bus_generic_attach(dev);
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return 0;
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}
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DRIVER_MODULE(irongate, root, irongate_driver, irongate_devclass, 0, 0);
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