139f7f9bf5
upcoming 3.3 release (branching and freezing expected in a few weeks). Preliminary release notes can be found at the usual location: <http://llvm.org/docs/ReleaseNotes.html> An MFC is planned once the actual 3.3 release is finished.
525 lines
16 KiB
C++
525 lines
16 KiB
C++
//===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class parses the Schedule.td file and produces an API that can be used
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// to reason about whether an instruction can be added to a packet on a VLIW
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// architecture. The class internally generates a deterministic finite
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// automaton (DFA) that models all possible mappings of machine instructions
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// to functional units as instructions are added to a packet.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenTarget.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <list>
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#include <map>
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#include <string>
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using namespace llvm;
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//
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// class DFAPacketizerEmitter: class that generates and prints out the DFA
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// for resource tracking.
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//
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namespace {
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class DFAPacketizerEmitter {
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private:
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std::string TargetName;
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//
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// allInsnClasses is the set of all possible resources consumed by an
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// InstrStage.
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//
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DenseSet<unsigned> allInsnClasses;
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RecordKeeper &Records;
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public:
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DFAPacketizerEmitter(RecordKeeper &R);
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//
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// collectAllInsnClasses: Populate allInsnClasses which is a set of units
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// used in each stage.
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//
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void collectAllInsnClasses(const std::string &Name,
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Record *ItinData,
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unsigned &NStages,
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raw_ostream &OS);
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void run(raw_ostream &OS);
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};
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} // End anonymous namespace.
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//
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//
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// State represents the usage of machine resources if the packet contains
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// a set of instruction classes.
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//
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// Specifically, currentState is a set of bit-masks.
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// The nth bit in a bit-mask indicates whether the nth resource is being used
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// by this state. The set of bit-masks in a state represent the different
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// possible outcomes of transitioning to this state.
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// For example: consider a two resource architecture: resource L and resource M
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// with three instruction classes: L, M, and L_or_M.
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// From the initial state (currentState = 0x00), if we add instruction class
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// L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
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// represents the possible resource states that can result from adding a L_or_M
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// instruction
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//
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// Another way of thinking about this transition is we are mapping a NDFA with
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// two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10].
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//
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// A State instance also contains a collection of transitions from that state:
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// a map from inputs to new states.
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//
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namespace {
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class State {
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public:
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static int currentStateNum;
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int stateNum;
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bool isInitial;
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std::set<unsigned> stateInfo;
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typedef std::map<unsigned, State *> TransitionMap;
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TransitionMap Transitions;
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State();
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State(const State &S);
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bool operator<(const State &s) const {
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return stateNum < s.stateNum;
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}
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//
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// canAddInsnClass - Returns true if an instruction of type InsnClass is a
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// valid transition from this state, i.e., can an instruction of type InsnClass
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// be added to the packet represented by this state.
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//
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions.
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//
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bool canAddInsnClass(unsigned InsnClass) const;
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//
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// AddInsnClass - Return all combinations of resource reservation
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// which are possible from this state (PossibleStates).
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//
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void AddInsnClass(unsigned InsnClass, std::set<unsigned> &PossibleStates);
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//
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// addTransition - Add a transition from this state given the input InsnClass
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//
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void addTransition(unsigned InsnClass, State *To);
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//
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// hasTransition - Returns true if there is a transition from this state
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// given the input InsnClass
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//
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bool hasTransition(unsigned InsnClass);
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};
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} // End anonymous namespace.
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//
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// class DFA: deterministic finite automaton for processor resource tracking.
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//
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namespace {
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class DFA {
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public:
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DFA();
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~DFA();
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// Set of states. Need to keep this sorted to emit the transition table.
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typedef std::set<State *, less_ptr<State> > StateSet;
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StateSet states;
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State *currentState;
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//
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// Modify the DFA.
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//
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void initialize();
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void addState(State *);
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//
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// writeTable: Print out a table representing the DFA.
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//
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void writeTableAndAPI(raw_ostream &OS, const std::string &ClassName);
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};
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} // End anonymous namespace.
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//
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// Constructors and destructors for State and DFA
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//
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State::State() :
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stateNum(currentStateNum++), isInitial(false) {}
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State::State(const State &S) :
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stateNum(currentStateNum++), isInitial(S.isInitial),
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stateInfo(S.stateInfo) {}
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DFA::DFA(): currentState(NULL) {}
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DFA::~DFA() {
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DeleteContainerPointers(states);
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}
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//
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// addTransition - Add a transition from this state given the input InsnClass
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//
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void State::addTransition(unsigned InsnClass, State *To) {
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assert(!Transitions.count(InsnClass) &&
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"Cannot have multiple transitions for the same input");
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Transitions[InsnClass] = To;
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}
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//
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// hasTransition - Returns true if there is a transition from this state
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// given the input InsnClass
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//
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bool State::hasTransition(unsigned InsnClass) {
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return Transitions.count(InsnClass) > 0;
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}
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//
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// AddInsnClass - Return all combinations of resource reservation
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// which are possible from this state (PossibleStates).
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//
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void State::AddInsnClass(unsigned InsnClass,
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std::set<unsigned> &PossibleStates) {
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//
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// Iterate over all resource states in currentState.
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//
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for (std::set<unsigned>::iterator SI = stateInfo.begin();
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SI != stateInfo.end(); ++SI) {
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unsigned thisState = *SI;
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//
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// Iterate over all possible resources used in InsnClass.
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// For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}.
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//
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DenseSet<unsigned> VisitedResourceStates;
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for (unsigned int j = 0; j < sizeof(InsnClass) * 8; ++j) {
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if ((0x1 << j) & InsnClass) {
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//
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// For each possible resource used in InsnClass, generate the
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// resource state if that resource was used.
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//
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unsigned ResultingResourceState = thisState | (0x1 << j);
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//
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// Check if the resulting resource state can be accommodated in this
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// packet.
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// We compute ResultingResourceState OR thisState.
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// If the result of the OR is different than thisState, it implies
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// that there is at least one resource that can be used to schedule
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// InsnClass in the current packet.
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// Insert ResultingResourceState into PossibleStates only if we haven't
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// processed ResultingResourceState before.
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//
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if ((ResultingResourceState != thisState) &&
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(VisitedResourceStates.count(ResultingResourceState) == 0)) {
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VisitedResourceStates.insert(ResultingResourceState);
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PossibleStates.insert(ResultingResourceState);
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}
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}
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}
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}
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}
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//
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// canAddInsnClass - Quickly verifies if an instruction of type InsnClass is a
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// valid transition from this state i.e., can an instruction of type InsnClass
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// be added to the packet represented by this state.
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//
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bool State::canAddInsnClass(unsigned InsnClass) const {
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for (std::set<unsigned>::const_iterator SI = stateInfo.begin();
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SI != stateInfo.end(); ++SI) {
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if (~*SI & InsnClass)
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return true;
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}
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return false;
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}
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void DFA::initialize() {
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assert(currentState && "Missing current state");
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currentState->isInitial = true;
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}
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void DFA::addState(State *S) {
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assert(!states.count(S) && "State already exists");
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states.insert(S);
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}
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int State::currentStateNum = 0;
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DFAPacketizerEmitter::DFAPacketizerEmitter(RecordKeeper &R):
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TargetName(CodeGenTarget(R).getName()),
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allInsnClasses(), Records(R) {}
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//
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// writeTableAndAPI - Print out a table representing the DFA and the
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// associated API to create a DFA packetizer.
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//
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// Format:
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// DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
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// transitions.
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// DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
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// the ith state.
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//
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//
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void DFA::writeTableAndAPI(raw_ostream &OS, const std::string &TargetName) {
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static const std::string SentinelEntry = "{-1, -1}";
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DFA::StateSet::iterator SI = states.begin();
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// This table provides a map to the beginning of the transitions for State s
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// in DFAStateInputTable.
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std::vector<int> StateEntry(states.size());
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OS << "namespace llvm {\n\n";
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OS << "const int " << TargetName << "DFAStateInputTable[][2] = {\n";
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// Tracks the total valid transitions encountered so far. It is used
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// to construct the StateEntry table.
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int ValidTransitions = 0;
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for (unsigned i = 0; i < states.size(); ++i, ++SI) {
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assert (((*SI)->stateNum == (int) i) && "Mismatch in state numbers");
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StateEntry[i] = ValidTransitions;
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for (State::TransitionMap::iterator
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II = (*SI)->Transitions.begin(), IE = (*SI)->Transitions.end();
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II != IE; ++II) {
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OS << "{" << II->first << ", "
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<< II->second->stateNum
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<< "}, ";
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}
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ValidTransitions += (*SI)->Transitions.size();
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// If there are no valid transitions from this stage, we need a sentinel
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// transition.
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if (ValidTransitions == StateEntry[i]) {
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OS << SentinelEntry << ",";
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++ValidTransitions;
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}
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OS << "\n";
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}
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// Print out a sentinel entry at the end of the StateInputTable. This is
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// needed to iterate over StateInputTable in DFAPacketizer::ReadTable()
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OS << SentinelEntry << "\n";
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OS << "};\n\n";
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OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
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// Multiply i by 2 since each entry in DFAStateInputTable is a set of
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// two numbers.
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for (unsigned i = 0; i < states.size(); ++i)
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OS << StateEntry[i] << ", ";
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// Print out the index to the sentinel entry in StateInputTable
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OS << ValidTransitions << ", ";
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OS << "\n};\n";
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OS << "} // namespace\n";
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//
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// Emit DFA Packetizer tables if the target is a VLIW machine.
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//
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std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
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OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
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OS << "namespace llvm {\n";
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OS << "DFAPacketizer *" << SubTargetClassName << "::"
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<< "createDFAPacketizer(const InstrItineraryData *IID) const {\n"
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<< " return new DFAPacketizer(IID, " << TargetName
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<< "DFAStateInputTable, " << TargetName << "DFAStateEntryTable);\n}\n\n";
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OS << "} // End llvm namespace \n";
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}
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//
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// collectAllInsnClasses - Populate allInsnClasses which is a set of units
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// used in each stage.
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//
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void DFAPacketizerEmitter::collectAllInsnClasses(const std::string &Name,
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Record *ItinData,
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unsigned &NStages,
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raw_ostream &OS) {
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// Collect processor itineraries.
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std::vector<Record*> ProcItinList =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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// If just no itinerary then don't bother.
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if (ProcItinList.size() < 2)
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return;
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std::map<std::string, unsigned> NameToBitsMap;
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// Parse functional units for all the itineraries.
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for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) {
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Record *Proc = ProcItinList[i];
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std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
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// Convert macros to bits for each stage.
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for (unsigned i = 0, N = FUs.size(); i < N; ++i)
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NameToBitsMap[FUs[i]->getName()] = (unsigned) (1U << i);
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}
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const std::vector<Record*> &StageList =
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ItinData->getValueAsListOfDefs("Stages");
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// The number of stages.
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NStages = StageList.size();
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// For each unit.
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unsigned UnitBitValue = 0;
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// Compute the bitwise or of each unit used in this stage.
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for (unsigned i = 0; i < NStages; ++i) {
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const Record *Stage = StageList[i];
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// Get unit list.
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const std::vector<Record*> &UnitList =
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Stage->getValueAsListOfDefs("Units");
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for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
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// Conduct bitwise or.
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std::string UnitName = UnitList[j]->getName();
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assert(NameToBitsMap.count(UnitName));
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UnitBitValue |= NameToBitsMap[UnitName];
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}
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if (UnitBitValue != 0)
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allInsnClasses.insert(UnitBitValue);
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}
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}
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//
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// Run the worklist algorithm to generate the DFA.
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//
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void DFAPacketizerEmitter::run(raw_ostream &OS) {
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// Collect processor iteraries.
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std::vector<Record*> ProcItinList =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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//
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// Collect the instruction classes.
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//
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for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
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Record *Proc = ProcItinList[i];
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// Get processor itinerary name.
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const std::string &Name = Proc->getName();
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// Skip default.
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if (Name == "NoItineraries")
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continue;
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// Sanity check for at least one instruction itinerary class.
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unsigned NItinClasses =
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Records.getAllDerivedDefinitions("InstrItinClass").size();
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if (NItinClasses == 0)
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return;
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// Get itinerary data list.
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std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
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// Collect instruction classes for all itinerary data.
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for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
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Record *ItinData = ItinDataList[j];
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unsigned NStages;
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collectAllInsnClasses(Name, ItinData, NStages, OS);
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}
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}
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//
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// Run a worklist algorithm to generate the DFA.
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//
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DFA D;
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State *Initial = new State;
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Initial->isInitial = true;
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Initial->stateInfo.insert(0x0);
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D.addState(Initial);
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SmallVector<State*, 32> WorkList;
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std::map<std::set<unsigned>, State*> Visited;
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WorkList.push_back(Initial);
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//
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// Worklist algorithm to create a DFA for processor resource tracking.
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// C = {set of InsnClasses}
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// Begin with initial node in worklist. Initial node does not have
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// any consumed resources,
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// ResourceState = 0x0
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// Visited = {}
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// While worklist != empty
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// S = first element of worklist
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// For every instruction class C
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// if we can accommodate C in S:
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// S' = state with resource states = {S Union C}
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// Add a new transition: S x C -> S'
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// If S' is not in Visited:
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// Add S' to worklist
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// Add S' to Visited
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//
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while (!WorkList.empty()) {
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State *current = WorkList.pop_back_val();
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for (DenseSet<unsigned>::iterator CI = allInsnClasses.begin(),
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CE = allInsnClasses.end(); CI != CE; ++CI) {
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unsigned InsnClass = *CI;
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std::set<unsigned> NewStateResources;
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//
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// If we haven't already created a transition for this input
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// and the state can accommodate this InsnClass, create a transition.
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//
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if (!current->hasTransition(InsnClass) &&
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current->canAddInsnClass(InsnClass)) {
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State *NewState = NULL;
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current->AddInsnClass(InsnClass, NewStateResources);
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assert(NewStateResources.size() && "New states must be generated");
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//
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// If we have seen this state before, then do not create a new state.
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//
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//
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std::map<std::set<unsigned>, State*>::iterator VI;
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if ((VI = Visited.find(NewStateResources)) != Visited.end())
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NewState = VI->second;
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else {
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NewState = new State;
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NewState->stateInfo = NewStateResources;
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D.addState(NewState);
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Visited[NewStateResources] = NewState;
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WorkList.push_back(NewState);
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}
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current->addTransition(InsnClass, NewState);
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}
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}
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}
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// Print out the table.
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D.writeTableAndAPI(OS, TargetName);
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}
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namespace llvm {
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void EmitDFAPacketizer(RecordKeeper &RK, raw_ostream &OS) {
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emitSourceFileHeader("Target DFA Packetizer Tables", OS);
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DFAPacketizerEmitter(RK).run(OS);
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}
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} // End llvm namespace
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