c49761dd57
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
492 lines
12 KiB
C
492 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2011 NetApp, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <machine/clock.h>
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#include <machine/cpufunc.h>
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#include <machine/md_var.h>
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#include <machine/pcb.h>
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#include <machine/specialreg.h>
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#include <machine/vmm.h>
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#include "vmx.h"
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#include "vmx_msr.h"
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static boolean_t
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vmx_ctl_allows_one_setting(uint64_t msr_val, int bitpos)
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{
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if (msr_val & (1UL << (bitpos + 32)))
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return (TRUE);
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else
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return (FALSE);
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}
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static boolean_t
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vmx_ctl_allows_zero_setting(uint64_t msr_val, int bitpos)
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{
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if ((msr_val & (1UL << bitpos)) == 0)
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return (TRUE);
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else
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return (FALSE);
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}
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uint32_t
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vmx_revision(void)
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{
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return (rdmsr(MSR_VMX_BASIC) & 0xffffffff);
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}
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/*
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* Generate a bitmask to be used for the VMCS execution control fields.
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*
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* The caller specifies what bits should be set to one in 'ones_mask'
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* and what bits should be set to zero in 'zeros_mask'. The don't-care
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* bits are set to the default value. The default values are obtained
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* based on "Algorithm 3" in Section 27.5.1 "Algorithms for Determining
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* VMX Capabilities".
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*
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* Returns zero on success and non-zero on error.
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*/
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int
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vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask,
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uint32_t zeros_mask, uint32_t *retval)
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{
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int i;
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uint64_t val, trueval;
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boolean_t true_ctls_avail, one_allowed, zero_allowed;
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/* We cannot ask the same bit to be set to both '1' and '0' */
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if ((ones_mask ^ zeros_mask) != (ones_mask | zeros_mask))
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return (EINVAL);
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if (rdmsr(MSR_VMX_BASIC) & (1UL << 55))
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true_ctls_avail = TRUE;
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else
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true_ctls_avail = FALSE;
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val = rdmsr(ctl_reg);
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if (true_ctls_avail)
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trueval = rdmsr(true_ctl_reg); /* step c */
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else
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trueval = val; /* step a */
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for (i = 0; i < 32; i++) {
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one_allowed = vmx_ctl_allows_one_setting(trueval, i);
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zero_allowed = vmx_ctl_allows_zero_setting(trueval, i);
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KASSERT(one_allowed || zero_allowed,
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("invalid zero/one setting for bit %d of ctl 0x%0x, "
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"truectl 0x%0x\n", i, ctl_reg, true_ctl_reg));
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if (zero_allowed && !one_allowed) { /* b(i),c(i) */
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if (ones_mask & (1 << i))
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return (EINVAL);
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*retval &= ~(1 << i);
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} else if (one_allowed && !zero_allowed) { /* b(i),c(i) */
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if (zeros_mask & (1 << i))
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return (EINVAL);
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*retval |= 1 << i;
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} else {
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if (zeros_mask & (1 << i)) /* b(ii),c(ii) */
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*retval &= ~(1 << i);
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else if (ones_mask & (1 << i)) /* b(ii), c(ii) */
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*retval |= 1 << i;
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else if (!true_ctls_avail)
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*retval &= ~(1 << i); /* b(iii) */
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else if (vmx_ctl_allows_zero_setting(val, i))/* c(iii)*/
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*retval &= ~(1 << i);
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else if (vmx_ctl_allows_one_setting(val, i)) /* c(iv) */
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*retval |= 1 << i;
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else {
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panic("vmx_set_ctlreg: unable to determine "
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"correct value of ctl bit %d for msr "
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"0x%0x and true msr 0x%0x", i, ctl_reg,
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true_ctl_reg);
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}
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}
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}
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return (0);
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}
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void
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msr_bitmap_initialize(char *bitmap)
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{
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memset(bitmap, 0xff, PAGE_SIZE);
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}
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int
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msr_bitmap_change_access(char *bitmap, u_int msr, int access)
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{
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int byte, bit;
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if (msr <= 0x00001FFF)
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byte = msr / 8;
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else if (msr >= 0xC0000000 && msr <= 0xC0001FFF)
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byte = 1024 + (msr - 0xC0000000) / 8;
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else
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return (EINVAL);
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bit = msr & 0x7;
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if (access & MSR_BITMAP_ACCESS_READ)
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bitmap[byte] &= ~(1 << bit);
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else
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bitmap[byte] |= 1 << bit;
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byte += 2048;
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if (access & MSR_BITMAP_ACCESS_WRITE)
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bitmap[byte] &= ~(1 << bit);
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else
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bitmap[byte] |= 1 << bit;
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return (0);
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}
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static uint64_t misc_enable;
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static uint64_t platform_info;
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static uint64_t turbo_ratio_limit;
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static uint64_t host_msrs[GUEST_MSR_NUM];
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static bool
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nehalem_cpu(void)
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{
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u_int family, model;
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/*
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* The family:model numbers belonging to the Nehalem microarchitecture
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* are documented in Section 35.5, Intel SDM dated Feb 2014.
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*/
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family = CPUID_TO_FAMILY(cpu_id);
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model = CPUID_TO_MODEL(cpu_id);
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if (family == 0x6) {
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switch (model) {
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case 0x1A:
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case 0x1E:
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case 0x1F:
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case 0x2E:
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return (true);
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default:
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break;
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}
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}
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return (false);
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}
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static bool
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westmere_cpu(void)
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{
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u_int family, model;
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/*
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* The family:model numbers belonging to the Westmere microarchitecture
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* are documented in Section 35.6, Intel SDM dated Feb 2014.
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*/
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family = CPUID_TO_FAMILY(cpu_id);
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model = CPUID_TO_MODEL(cpu_id);
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if (family == 0x6) {
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switch (model) {
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case 0x25:
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case 0x2C:
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return (true);
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default:
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break;
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}
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}
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return (false);
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}
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static bool
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pat_valid(uint64_t val)
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{
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int i, pa;
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/*
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* From Intel SDM: Table "Memory Types That Can Be Encoded With PAT"
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*
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* Extract PA0 through PA7 and validate that each one encodes a
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* valid memory type.
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*/
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for (i = 0; i < 8; i++) {
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pa = (val >> (i * 8)) & 0xff;
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if (pa == 2 || pa == 3 || pa >= 8)
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return (false);
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}
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return (true);
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}
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void
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vmx_msr_init(void)
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{
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uint64_t bus_freq, ratio;
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int i;
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/*
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* It is safe to cache the values of the following MSRs because
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* they don't change based on curcpu, curproc or curthread.
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*/
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host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);
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host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);
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host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);
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host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);
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/*
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* Initialize emulated MSRs
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*/
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misc_enable = rdmsr(MSR_IA32_MISC_ENABLE);
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/*
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* Set mandatory bits
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* 11: branch trace disabled
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* 12: PEBS unavailable
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* Clear unsupported features
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* 16: SpeedStep enable
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* 18: enable MONITOR FSM
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*/
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misc_enable |= (1 << 12) | (1 << 11);
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misc_enable &= ~((1 << 18) | (1 << 16));
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if (nehalem_cpu() || westmere_cpu())
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bus_freq = 133330000; /* 133Mhz */
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else
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bus_freq = 100000000; /* 100Mhz */
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/*
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* XXXtime
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* The ratio should really be based on the virtual TSC frequency as
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* opposed to the host TSC.
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*/
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ratio = (tsc_freq / bus_freq) & 0xff;
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/*
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* The register definition is based on the micro-architecture
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* but the following bits are always the same:
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* [15:8] Maximum Non-Turbo Ratio
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* [28] Programmable Ratio Limit for Turbo Mode
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* [29] Programmable TDC-TDP Limit for Turbo Mode
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* [47:40] Maximum Efficiency Ratio
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*
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* The other bits can be safely set to 0 on all
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* micro-architectures up to Haswell.
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*/
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platform_info = (ratio << 8) | (ratio << 40);
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/*
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* The number of valid bits in the MSR_TURBO_RATIO_LIMITx register is
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* dependent on the maximum cores per package supported by the micro-
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* architecture. For e.g., Westmere supports 6 cores per package and
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* uses the low 48 bits. Sandybridge support 8 cores per package and
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* uses up all 64 bits.
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*
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* However, the unused bits are reserved so we pretend that all bits
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* in this MSR are valid.
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*/
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for (i = 0; i < 8; i++)
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turbo_ratio_limit = (turbo_ratio_limit << 8) | ratio;
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}
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void
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vmx_msr_guest_init(struct vmx *vmx, int vcpuid)
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{
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uint64_t *guest_msrs;
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guest_msrs = vmx->guest_msrs[vcpuid];
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/*
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* The permissions bitmap is shared between all vcpus so initialize it
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* once when initializing the vBSP.
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*/
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if (vcpuid == 0) {
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guest_msr_rw(vmx, MSR_LSTAR);
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guest_msr_rw(vmx, MSR_CSTAR);
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guest_msr_rw(vmx, MSR_STAR);
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guest_msr_rw(vmx, MSR_SF_MASK);
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guest_msr_rw(vmx, MSR_KGSBASE);
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}
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/*
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* Initialize guest IA32_PAT MSR with default value after reset.
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*/
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guest_msrs[IDX_MSR_PAT] = PAT_VALUE(0, PAT_WRITE_BACK) |
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PAT_VALUE(1, PAT_WRITE_THROUGH) |
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PAT_VALUE(2, PAT_UNCACHED) |
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PAT_VALUE(3, PAT_UNCACHEABLE) |
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PAT_VALUE(4, PAT_WRITE_BACK) |
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PAT_VALUE(5, PAT_WRITE_THROUGH) |
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PAT_VALUE(6, PAT_UNCACHED) |
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PAT_VALUE(7, PAT_UNCACHEABLE);
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return;
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}
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void
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vmx_msr_guest_enter(struct vmx *vmx, int vcpuid)
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{
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uint64_t *guest_msrs = vmx->guest_msrs[vcpuid];
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/* Save host MSRs (in particular, KGSBASE) and restore guest MSRs */
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update_pcb_bases(curpcb);
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wrmsr(MSR_LSTAR, guest_msrs[IDX_MSR_LSTAR]);
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wrmsr(MSR_CSTAR, guest_msrs[IDX_MSR_CSTAR]);
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wrmsr(MSR_STAR, guest_msrs[IDX_MSR_STAR]);
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wrmsr(MSR_SF_MASK, guest_msrs[IDX_MSR_SF_MASK]);
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wrmsr(MSR_KGSBASE, guest_msrs[IDX_MSR_KGSBASE]);
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}
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void
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vmx_msr_guest_exit(struct vmx *vmx, int vcpuid)
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{
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uint64_t *guest_msrs = vmx->guest_msrs[vcpuid];
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/* Save guest MSRs */
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guest_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);
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guest_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);
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guest_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);
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guest_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);
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guest_msrs[IDX_MSR_KGSBASE] = rdmsr(MSR_KGSBASE);
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/* Restore host MSRs */
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wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]);
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wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]);
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wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]);
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wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]);
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/* MSR_KGSBASE will be restored on the way back to userspace */
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}
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int
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vmx_rdmsr(struct vmx *vmx, int vcpuid, u_int num, uint64_t *val, bool *retu)
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{
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const uint64_t *guest_msrs;
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int error;
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guest_msrs = vmx->guest_msrs[vcpuid];
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error = 0;
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switch (num) {
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case MSR_MCG_CAP:
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case MSR_MCG_STATUS:
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*val = 0;
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break;
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case MSR_MTRRcap:
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case MSR_MTRRdefType:
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case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8:
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case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
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case MSR_MTRR64kBase:
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*val = 0;
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break;
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case MSR_IA32_MISC_ENABLE:
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*val = misc_enable;
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break;
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case MSR_PLATFORM_INFO:
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*val = platform_info;
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break;
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case MSR_TURBO_RATIO_LIMIT:
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case MSR_TURBO_RATIO_LIMIT1:
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*val = turbo_ratio_limit;
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break;
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case MSR_PAT:
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*val = guest_msrs[IDX_MSR_PAT];
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break;
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default:
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error = EINVAL;
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break;
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}
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return (error);
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}
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int
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vmx_wrmsr(struct vmx *vmx, int vcpuid, u_int num, uint64_t val, bool *retu)
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{
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uint64_t *guest_msrs;
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uint64_t changed;
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int error;
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guest_msrs = vmx->guest_msrs[vcpuid];
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error = 0;
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switch (num) {
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case MSR_MCG_CAP:
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case MSR_MCG_STATUS:
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break; /* ignore writes */
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case MSR_MTRRcap:
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vm_inject_gp(vmx->vm, vcpuid);
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break;
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case MSR_MTRRdefType:
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case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8:
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case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1:
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case MSR_MTRR64kBase:
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break; /* Ignore writes */
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case MSR_IA32_MISC_ENABLE:
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changed = val ^ misc_enable;
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/*
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* If the host has disabled the NX feature then the guest
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* also cannot use it. However, a Linux guest will try to
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* enable the NX feature by writing to the MISC_ENABLE MSR.
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*
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* This can be safely ignored because the memory management
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* code looks at CPUID.80000001H:EDX.NX to check if the
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* functionality is actually enabled.
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*/
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changed &= ~(1UL << 34);
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/*
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* Punt to userspace if any other bits are being modified.
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*/
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if (changed)
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error = EINVAL;
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break;
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case MSR_PAT:
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if (pat_valid(val))
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guest_msrs[IDX_MSR_PAT] = val;
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else
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vm_inject_gp(vmx->vm, vcpuid);
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break;
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case MSR_TSC:
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error = vmx_set_tsc_offset(vmx, vcpuid, val - rdtsc());
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break;
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default:
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error = EINVAL;
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break;
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}
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return (error);
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}
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