a745246822
This supports e500v1, e500v2, and e500mc. Tested only on e500v2, but the performance counters are identical across all, with e500mc having some additional events. Relnotes: Yes
756 lines
15 KiB
ArmAsm
756 lines
15 KiB
ArmAsm
/*-
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* Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
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* Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include "assym.s"
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#include "opt_hwpmc_hooks.h"
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#include <machine/asm.h>
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#include <machine/hid.h>
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#include <machine/param.h>
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#include <machine/spr.h>
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#include <machine/pte.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <machine/tlb.h>
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#define TMPSTACKSZ 16384
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.text
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.globl btext
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btext:
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/*
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* This symbol is here for the benefit of kvm_mkdb, and is supposed to
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* mark the start of kernel text.
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*/
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.globl kernel_text
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kernel_text:
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/*
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* Startup entry. Note, this must be the first thing in the text segment!
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*/
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.text
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.globl __start
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__start:
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/*
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* Assumptions on the boot loader:
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* - system memory starts from physical address 0
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* - it's mapped by a single TBL1 entry
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* - TLB1 mapping is 1:1 pa to va
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* - kernel is loaded at 16MB boundary
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* - all PID registers are set to the same value
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* - CPU is running in AS=0
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*
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* Registers contents provided by the loader(8):
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* r1 : stack pointer
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* r3 : metadata pointer
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*
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* We rearrange the TLB1 layout as follows:
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* - find TLB1 entry we started in
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* - make sure it's protected, ivalidate other entries
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* - create temp entry in the second AS (make sure it's not TLB[1])
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* - switch to temp mapping
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* - map 16MB of RAM in TLB1[1]
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* - use AS=1, set EPN to KERNBASE and RPN to kernel load address
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* - switch to to TLB1[1] mapping
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* - invalidate temp mapping
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*
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* locore registers use:
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* r1 : stack pointer
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* r2 : trace pointer (AP only, for early diagnostics)
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* r3-r27 : scratch registers
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* r28 : temp TLB1 entry
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* r29 : initial TLB1 entry we started in
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* r30-r31 : arguments (metadata pointer)
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*/
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/*
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* Keep arguments in r30 & r31 for later use.
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*/
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mr %r30, %r3
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mr %r31, %r4
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/*
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* Initial cleanup
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*/
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li %r3, PSL_DE /* Keep debug exceptions for CodeWarrior. */
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mtmsr %r3
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isync
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lis %r3, HID0_E500_DEFAULT_SET@h
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ori %r3, %r3, HID0_E500_DEFAULT_SET@l
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mtspr SPR_HID0, %r3
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isync
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lis %r3, HID1_E500_DEFAULT_SET@h
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ori %r3, %r3, HID1_E500_DEFAULT_SET@l
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mtspr SPR_HID1, %r3
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isync
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/* Invalidate all entries in TLB0 */
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li %r3, 0
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bl tlb_inval_all
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cmpwi %r30, 0
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beq done_mapping
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/*
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* Locate the TLB1 entry that maps this code
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*/
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bl 1f
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1: mflr %r3
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bl tlb1_find_current /* the entry found is returned in r29 */
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bl tlb1_inval_all_but_current
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/*
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* Create temporary mapping in AS=1 and switch to it
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*/
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addi %r3, %r29, 1
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bl tlb1_temp_mapping_as1
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mfmsr %r3
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ori %r3, %r3, (PSL_IS | PSL_DS)
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bl 2f
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2: mflr %r4
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addi %r4, %r4, 20
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi /* Switch context */
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/*
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* Invalidate initial entry
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*/
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mr %r3, %r29
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bl tlb1_inval_entry
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/*
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* Setup final mapping in TLB1[1] and switch to it
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*/
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/* Final kernel mapping, map in 16 MB of RAM */
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lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
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li %r4, 0 /* Entry 0 */
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rlwimi %r3, %r4, 16, 12, 15
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mtspr SPR_MAS0, %r3
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isync
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li %r3, (TLB_SIZE_64M << MAS1_TSIZE_SHIFT)@l
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oris %r3, %r3, (MAS1_VALID | MAS1_IPROT)@h
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mtspr SPR_MAS1, %r3 /* note TS was not filled, so it's TS=0 */
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isync
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lis %r3, KERNBASE@h
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ori %r3, %r3, KERNBASE@l /* EPN = KERNBASE */
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#ifdef SMP
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ori %r3, %r3, MAS2_M@l /* WIMGE = 0b00100 */
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#endif
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mtspr SPR_MAS2, %r3
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isync
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/* Discover phys load address */
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bl 3f
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3: mflr %r4 /* Use current address */
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rlwinm %r4, %r4, 0, 0, 7 /* 16MB alignment mask */
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ori %r4, %r4, (MAS3_SX | MAS3_SW | MAS3_SR)@l
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mtspr SPR_MAS3, %r4 /* Set RPN and protection */
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isync
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tlbwe
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isync
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msync
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/* Switch to the above TLB1[1] mapping */
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bl 4f
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4: mflr %r4
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rlwinm %r4, %r4, 0, 8, 31 /* Current offset from kernel load address */
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rlwinm %r3, %r3, 0, 0, 19
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add %r4, %r4, %r3 /* Convert to kernel virtual address */
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addi %r4, %r4, 36
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li %r3, PSL_DE /* Note AS=0 */
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi
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/*
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* Invalidate temp mapping
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*/
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mr %r3, %r28
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bl tlb1_inval_entry
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done_mapping:
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/*
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* Setup a temporary stack
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*/
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bl 1f
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.long tmpstack-.
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1: mflr %r1
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lwz %r2,0(%r1)
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add %r1,%r1,%r2
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addi %r1, %r1, (TMPSTACKSZ - 16)
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/*
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* Relocate kernel
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*/
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bl 1f
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.long _DYNAMIC-.
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.long _GLOBAL_OFFSET_TABLE_-.
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1: mflr %r5
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lwz %r3,0(%r5) /* _DYNAMIC in %r3 */
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add %r3,%r3,%r5
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lwz %r4,4(%r5) /* GOT pointer */
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add %r4,%r4,%r5
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lwz %r4,4(%r4) /* got[0] is _DYNAMIC link addr */
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subf %r4,%r4,%r3 /* subtract to calculate relocbase */
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bl elf_reloc_self
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/*
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* Initialise exception vector offsets
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*/
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bl ivor_setup
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/*
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* Set up arguments and jump to system initialization code
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*/
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mr %r3, %r30
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mr %r4, %r31
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/* Prepare core */
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bl booke_init
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/* Switch to thread0.td_kstack now */
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mr %r1, %r3
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li %r3, 0
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stw %r3, 0(%r1)
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/* Machine independet part, does not return */
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bl mi_startup
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/* NOT REACHED */
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5: b 5b
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#ifdef SMP
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/************************************************************************/
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/* AP Boot page */
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/************************************************************************/
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.text
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.globl __boot_page
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.align 12
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__boot_page:
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bl 1f
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.globl bp_ntlb1s
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bp_ntlb1s:
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.long 0
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.globl bp_tlb1
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bp_tlb1:
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.space 4 * 3 * 16
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.globl bp_tlb1_end
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bp_tlb1_end:
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/*
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* Initial configuration
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*/
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1: mflr %r31 /* r31 hold the address of bp_ntlb1s */
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/* Set HIDs */
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lis %r3, HID0_E500_DEFAULT_SET@h
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ori %r3, %r3, HID0_E500_DEFAULT_SET@l
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mtspr SPR_HID0, %r3
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isync
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lis %r3, HID1_E500_DEFAULT_SET@h
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ori %r3, %r3, HID1_E500_DEFAULT_SET@l
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mtspr SPR_HID1, %r3
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isync
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/* Enable branch prediction */
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li %r3, BUCSR_BPEN
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mtspr SPR_BUCSR, %r3
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isync
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/* Invalidate all entries in TLB0 */
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li %r3, 0
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bl tlb_inval_all
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/*
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* Find TLB1 entry which is translating us now
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*/
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bl 2f
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2: mflr %r3
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bl tlb1_find_current /* the entry number found is in r29 */
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bl tlb1_inval_all_but_current
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/*
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* Create temporary translation in AS=1 and switch to it
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*/
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lwz %r3, 0(%r31)
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bl tlb1_temp_mapping_as1
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mfmsr %r3
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ori %r3, %r3, (PSL_IS | PSL_DS)
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bl 3f
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3: mflr %r4
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addi %r4, %r4, 20
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mtspr SPR_SRR0, %r4
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mtspr SPR_SRR1, %r3
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rfi /* Switch context */
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/*
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* Invalidate initial entry
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*/
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mr %r3, %r29
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bl tlb1_inval_entry
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/*
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* Setup final mapping in TLB1[1] and switch to it
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*/
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lwz %r6, 0(%r31)
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addi %r5, %r31, 4
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li %r4, 0
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4: lis %r3, MAS0_TLBSEL1@h
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rlwimi %r3, %r4, 16, 12, 15
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mtspr SPR_MAS0, %r3
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isync
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lwz %r3, 0(%r5)
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mtspr SPR_MAS1, %r3
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isync
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lwz %r3, 4(%r5)
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mtspr SPR_MAS2, %r3
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isync
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lwz %r3, 8(%r5)
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mtspr SPR_MAS3, %r3
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isync
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tlbwe
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isync
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msync
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addi %r5, %r5, 12
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addi %r4, %r4, 1
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cmpw %r4, %r6
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blt 4b
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/* Switch to the final mapping */
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bl 5f
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.long __boot_page-.
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5: mflr %r5
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lwz %r3,0(%r3)
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add %r5,%r5,%r3 /* __boot_page in r5 */
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bl 6f
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6: mflr %r3
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rlwinm %r3, %r3, 0, 0xfff /* Offset from boot page start */
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add %r3, %r3, %r5 /* Make this virtual address */
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addi %r3, %r3, 32
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li %r4, 0 /* Note AS=0 */
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mtspr SPR_SRR0, %r3
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mtspr SPR_SRR1, %r4
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rfi
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/*
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* At this point we're running at virtual addresses KERNBASE and beyond so
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* it's allowed to directly access all locations the kernel was linked
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* against.
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*/
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/*
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* Invalidate temp mapping
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*/
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mr %r3, %r28
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bl tlb1_inval_entry
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/*
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* Setup a temporary stack
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*/
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bl 1f
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.long tmpstack-.
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1: mflr %r1
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lwz %r2,0(%r1)
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add %r1,%r1,%r2
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addi %r1, %r1, (TMPSTACKSZ - 16)
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/*
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* Initialise exception vector offsets
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*/
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bl ivor_setup
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/*
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* Assign our pcpu instance
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*/
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bl 1f
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.long ap_pcpu-.
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1: mflr %r4
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lwz %r3, 0(%r4)
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add %r3, %r3, %r4
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lwz %r3, 0(%r3)
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mtsprg0 %r3
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bl pmap_bootstrap_ap
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bl cpudep_ap_bootstrap
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/* Switch to the idle thread's kstack */
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mr %r1, %r3
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bl machdep_ap_bootstrap
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/* NOT REACHED */
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6: b 6b
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#endif /* SMP */
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/*
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* Invalidate all entries in the given TLB.
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*
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* r3 TLBSEL
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*/
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tlb_inval_all:
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rlwinm %r3, %r3, 3, 0x18 /* TLBSEL */
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ori %r3, %r3, 0x4 /* INVALL */
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tlbivax 0, %r3
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isync
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msync
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tlbsync
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msync
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blr
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/*
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* expects address to look up in r3, returns entry number in r29
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*
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* FIXME: the hidden assumption is we are now running in AS=0, but we should
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* retrieve actual AS from MSR[IS|DS] and put it in MAS6[SAS]
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*/
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tlb1_find_current:
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mfspr %r17, SPR_PID0
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slwi %r17, %r17, MAS6_SPID0_SHIFT
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mtspr SPR_MAS6, %r17
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isync
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tlbsx 0, %r3
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mfspr %r17, SPR_MAS0
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rlwinm %r29, %r17, 16, 20, 31 /* MAS0[ESEL] -> r29 */
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/* Make sure we have IPROT set on the entry */
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mfspr %r17, SPR_MAS1
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oris %r17, %r17, MAS1_IPROT@h
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mtspr SPR_MAS1, %r17
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isync
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tlbwe
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isync
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msync
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blr
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/*
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* Invalidates a single entry in TLB1.
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*
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* r3 ESEL
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* r4-r5 scratched
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*/
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tlb1_inval_entry:
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lis %r4, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r4, %r3, 16, 12, 15 /* Select our entry */
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mtspr SPR_MAS0, %r4
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isync
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tlbre
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li %r5, 0 /* MAS1[V] = 0 */
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mtspr SPR_MAS1, %r5
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isync
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tlbwe
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isync
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msync
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blr
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/*
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* r3 entry of temp translation
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* r29 entry of current translation
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* r28 returns temp entry passed in r3
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* r4-r5 scratched
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*/
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tlb1_temp_mapping_as1:
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mr %r28, %r3
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/* Read our current translation */
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lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r3, %r29, 16, 12, 15 /* Select our current entry */
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mtspr SPR_MAS0, %r3
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isync
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tlbre
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/* Prepare and write temp entry */
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lis %r3, MAS0_TLBSEL1@h /* Select TLB1 */
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rlwimi %r3, %r28, 16, 12, 15 /* Select temp entry */
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mtspr SPR_MAS0, %r3
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isync
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mfspr %r5, SPR_MAS1
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li %r4, 1 /* AS=1 */
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rlwimi %r5, %r4, 12, 19, 19
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li %r4, 0 /* Global mapping, TID=0 */
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rlwimi %r5, %r4, 16, 8, 15
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oris %r5, %r5, (MAS1_VALID | MAS1_IPROT)@h
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mtspr SPR_MAS1, %r5
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isync
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tlbwe
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isync
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msync
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blr
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/*
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* Loops over TLB1, invalidates all entries skipping the one which currently
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* maps this code.
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*
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* r29 current entry
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* r3-r5 scratched
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*/
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tlb1_inval_all_but_current:
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mr %r6, %r3
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mfspr %r3, SPR_TLB1CFG /* Get number of entries */
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andi. %r3, %r3, TLBCFG_NENTRY_MASK@l
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li %r4, 0 /* Start from Entry 0 */
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1: lis %r5, MAS0_TLBSEL1@h
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rlwimi %r5, %r4, 16, 12, 15
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mtspr SPR_MAS0, %r5
|
|
isync
|
|
tlbre
|
|
mfspr %r5, SPR_MAS1
|
|
cmpw %r4, %r29 /* our current entry? */
|
|
beq 2f
|
|
rlwinm %r5, %r5, 0, 2, 31 /* clear VALID and IPROT bits */
|
|
mtspr SPR_MAS1, %r5
|
|
isync
|
|
tlbwe
|
|
isync
|
|
msync
|
|
2: addi %r4, %r4, 1
|
|
cmpw %r4, %r3 /* Check if this is the last entry */
|
|
bne 1b
|
|
blr
|
|
|
|
#ifdef SMP
|
|
__boot_page_padding:
|
|
/*
|
|
* Boot page needs to be exactly 4K, with the last word of this page
|
|
* acting as the reset vector, so we need to stuff the remainder.
|
|
* Upon release from holdoff CPU fetches the last word of the boot
|
|
* page.
|
|
*/
|
|
.space 4092 - (__boot_page_padding - __boot_page)
|
|
b __boot_page
|
|
#endif /* SMP */
|
|
|
|
/************************************************************************/
|
|
/* locore subroutines */
|
|
/************************************************************************/
|
|
|
|
/*
|
|
* void tid_flush(tlbtid_t tid);
|
|
*
|
|
* Invalidate all TLB0 entries which match the given TID. Note this is
|
|
* dedicated for cases when invalidation(s) should NOT be propagated to other
|
|
* CPUs.
|
|
*
|
|
* void tid_flush(tlbtid_t tid, int tlb0_ways, int tlb0_entries_per_way);
|
|
*
|
|
* XXX: why isn't this in C?
|
|
*/
|
|
ENTRY(tid_flush)
|
|
cmpwi %r3, TID_KERNEL
|
|
beq tid_flush_end /* don't evict kernel translations */
|
|
|
|
/* Disable interrupts */
|
|
mfmsr %r10
|
|
wrteei 0
|
|
|
|
li %r6, 0 /* ways counter */
|
|
loop_ways:
|
|
li %r7, 0 /* entries [per way] counter */
|
|
loop_entries:
|
|
/* Select TLB0 and ESEL (way) */
|
|
lis %r8, MAS0_TLBSEL0@h
|
|
rlwimi %r8, %r6, 16, 14, 15
|
|
mtspr SPR_MAS0, %r8
|
|
isync
|
|
|
|
/* Select EPN (entry within the way) */
|
|
rlwinm %r8, %r7, 12, 13, 19
|
|
mtspr SPR_MAS2, %r8
|
|
isync
|
|
tlbre
|
|
|
|
/* Check if valid entry */
|
|
mfspr %r8, SPR_MAS1
|
|
andis. %r9, %r8, MAS1_VALID@h
|
|
beq next_entry /* invalid entry */
|
|
|
|
/* Check if this is our TID */
|
|
rlwinm %r9, %r8, 16, 24, 31
|
|
|
|
cmplw %r9, %r3
|
|
bne next_entry /* not our TID */
|
|
|
|
/* Clear VALID bit */
|
|
rlwinm %r8, %r8, 0, 1, 31
|
|
mtspr SPR_MAS1, %r8
|
|
isync
|
|
tlbwe
|
|
isync
|
|
msync
|
|
|
|
next_entry:
|
|
addi %r7, %r7, 1
|
|
cmpw %r7, %r5
|
|
bne loop_entries
|
|
|
|
/* Next way */
|
|
addi %r6, %r6, 1
|
|
cmpw %r6, %r4
|
|
bne loop_ways
|
|
|
|
/* Restore MSR (possibly re-enable interrupts) */
|
|
mtmsr %r10
|
|
isync
|
|
|
|
tid_flush_end:
|
|
blr
|
|
|
|
/*
|
|
* Cache disable/enable/inval sequences according
|
|
* to section 2.16 of E500CORE RM.
|
|
*/
|
|
ENTRY(dcache_inval)
|
|
/* Invalidate d-cache */
|
|
mfspr %r3, SPR_L1CSR0
|
|
ori %r3, %r3, (L1CSR0_DCFI | L1CSR0_DCLFR)@l
|
|
msync
|
|
isync
|
|
mtspr SPR_L1CSR0, %r3
|
|
isync
|
|
1: mfspr %r3, SPR_L1CSR0
|
|
andi. %r3, %r3, L1CSR0_DCFI
|
|
bne 1b
|
|
blr
|
|
|
|
ENTRY(dcache_disable)
|
|
/* Disable d-cache */
|
|
mfspr %r3, SPR_L1CSR0
|
|
li %r4, L1CSR0_DCE@l
|
|
not %r4, %r4
|
|
and %r3, %r3, %r4
|
|
msync
|
|
isync
|
|
mtspr SPR_L1CSR0, %r3
|
|
isync
|
|
blr
|
|
|
|
ENTRY(dcache_enable)
|
|
/* Enable d-cache */
|
|
mfspr %r3, SPR_L1CSR0
|
|
oris %r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@h
|
|
ori %r3, %r3, (L1CSR0_DCPE | L1CSR0_DCE)@l
|
|
msync
|
|
isync
|
|
mtspr SPR_L1CSR0, %r3
|
|
isync
|
|
blr
|
|
|
|
ENTRY(icache_inval)
|
|
/* Invalidate i-cache */
|
|
mfspr %r3, SPR_L1CSR1
|
|
ori %r3, %r3, (L1CSR1_ICFI | L1CSR1_ICLFR)@l
|
|
isync
|
|
mtspr SPR_L1CSR1, %r3
|
|
isync
|
|
1: mfspr %r3, SPR_L1CSR1
|
|
andi. %r3, %r3, L1CSR1_ICFI
|
|
bne 1b
|
|
blr
|
|
|
|
ENTRY(icache_disable)
|
|
/* Disable i-cache */
|
|
mfspr %r3, SPR_L1CSR1
|
|
li %r4, L1CSR1_ICE@l
|
|
not %r4, %r4
|
|
and %r3, %r3, %r4
|
|
isync
|
|
mtspr SPR_L1CSR1, %r3
|
|
isync
|
|
blr
|
|
|
|
ENTRY(icache_enable)
|
|
/* Enable i-cache */
|
|
mfspr %r3, SPR_L1CSR1
|
|
oris %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@h
|
|
ori %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@l
|
|
isync
|
|
mtspr SPR_L1CSR1, %r3
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* int setfault()
|
|
*
|
|
* Similar to setjmp to setup for handling faults on accesses to user memory.
|
|
* Any routine using this may only call bcopy, either the form below,
|
|
* or the (currently used) C code optimized, so it doesn't use any non-volatile
|
|
* registers.
|
|
*/
|
|
.globl setfault
|
|
setfault:
|
|
mflr %r0
|
|
mfsprg0 %r4
|
|
lwz %r4, TD_PCB(%r2)
|
|
stw %r3, PCB_ONFAULT(%r4)
|
|
mfcr %r10
|
|
stw %r0, 0(%r3)
|
|
stw %r1, 4(%r3)
|
|
stw %r2, 8(%r3)
|
|
stmw %r13, 12(%r3) /* store CR, CTR, XER, [r13 .. r31] */
|
|
li %r3, 0 /* return FALSE */
|
|
blr
|
|
|
|
/************************************************************************/
|
|
/* Data section */
|
|
/************************************************************************/
|
|
.data
|
|
.align 3
|
|
GLOBAL(__startkernel)
|
|
.long begin
|
|
GLOBAL(__endkernel)
|
|
.long end
|
|
.align 4
|
|
tmpstack:
|
|
.space TMPSTACKSZ
|
|
tmpstackbound:
|
|
.space 10240 /* XXX: this really should not be necessary */
|
|
|
|
/*
|
|
* Compiled KERNBASE locations
|
|
*/
|
|
.globl kernbase
|
|
.set kernbase, KERNBASE
|
|
|
|
#include <powerpc/booke/trap_subr.S>
|