98f9879242
and it's associated state variables: icu_lock with the name "icu". This renames the imen_mtx for x86 SMP, but also uses the lock to protect access to the 8259 PIC on x86 UP. This also adds an appropriate lock to the various Alpha chipsets which fixes problems with Alpha SMP machines dropping interrupts with an SMP kernel.
675 lines
18 KiB
C
675 lines
18 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)isa.c 7.2 (Berkeley) 5/13/91
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* $FreeBSD$
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*/
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#include "opt_auto_eoi.h"
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#include "opt_isa.h"
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#include "opt_mca.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/errno.h>
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#include <sys/interrupt.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/syslog.h>
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#include <sys/systm.h>
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#include <sys/unistd.h>
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#include <machine/md_var.h>
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#include <machine/segments.h>
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#if defined(APIC_IO)
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#include <machine/smptests.h> /** FAST_HI */
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#include <machine/smp.h>
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#include <machine/resource.h>
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#endif /* APIC_IO */
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#ifdef PC98
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#include <pc98/pc98/pc98.h>
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#include <pc98/pc98/pc98_machdep.h>
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#include <pc98/pc98/epsonio.h>
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#else
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#include <i386/isa/isa.h>
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#endif
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#include <i386/isa/icu.h>
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#ifdef DEV_ISA
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#include <isa/isavar.h>
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#endif
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#include <i386/isa/intr_machdep.h>
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#include <sys/interrupt.h>
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#ifdef APIC_IO
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#include <machine/clock.h>
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#endif
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#ifdef DEV_MCA
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#include <i386/isa/mca_machdep.h>
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#endif
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/*
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* Per-interrupt data.
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*/
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u_long *intr_countp[ICU_LEN]; /* pointers to interrupt counters */
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driver_intr_t *intr_handler[ICU_LEN]; /* first level interrupt handler */
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struct ithd *ithds[ICU_LEN]; /* real interrupt handler */
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void *intr_unit[ICU_LEN];
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static struct mtx ithds_table_lock; /* protect the ithds table */
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static inthand_t *fastintr[ICU_LEN] = {
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&IDTVEC(fastintr0), &IDTVEC(fastintr1),
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&IDTVEC(fastintr2), &IDTVEC(fastintr3),
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&IDTVEC(fastintr4), &IDTVEC(fastintr5),
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&IDTVEC(fastintr6), &IDTVEC(fastintr7),
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&IDTVEC(fastintr8), &IDTVEC(fastintr9),
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&IDTVEC(fastintr10), &IDTVEC(fastintr11),
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&IDTVEC(fastintr12), &IDTVEC(fastintr13),
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&IDTVEC(fastintr14), &IDTVEC(fastintr15),
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#if defined(APIC_IO)
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&IDTVEC(fastintr16), &IDTVEC(fastintr17),
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&IDTVEC(fastintr18), &IDTVEC(fastintr19),
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&IDTVEC(fastintr20), &IDTVEC(fastintr21),
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&IDTVEC(fastintr22), &IDTVEC(fastintr23),
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&IDTVEC(fastintr24), &IDTVEC(fastintr25),
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&IDTVEC(fastintr26), &IDTVEC(fastintr27),
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&IDTVEC(fastintr28), &IDTVEC(fastintr29),
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&IDTVEC(fastintr30), &IDTVEC(fastintr31),
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#endif /* APIC_IO */
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};
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static inthand_t *slowintr[ICU_LEN] = {
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&IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
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&IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
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&IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
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&IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15),
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#if defined(APIC_IO)
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&IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19),
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&IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23),
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&IDTVEC(intr24), &IDTVEC(intr25), &IDTVEC(intr26), &IDTVEC(intr27),
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&IDTVEC(intr28), &IDTVEC(intr29), &IDTVEC(intr30), &IDTVEC(intr31),
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#endif /* APIC_IO */
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};
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static driver_intr_t isa_strayintr;
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static void ithds_init(void *dummy);
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static void ithread_enable(int vector);
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static void ithread_disable(int vector);
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static void init_i8259(void);
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#ifdef PC98
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#define NMI_PARITY 0x04
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#define NMI_EPARITY 0x02
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#else
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#define NMI_PARITY (1 << 7)
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#define NMI_IOCHAN (1 << 6)
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#define ENMI_WATCHDOG (1 << 7)
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#define ENMI_BUSTIMER (1 << 6)
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#define ENMI_IOSTATUS (1 << 5)
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#endif
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/*
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* Bus attachment for the ISA PIC.
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*/
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static struct isa_pnp_id atpic_ids[] = {
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{ 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
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{ 0 }
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};
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static int
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atpic_probe(device_t dev)
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{
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int result;
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if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids)) <= 0)
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device_quiet(dev);
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return(result);
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}
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/*
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* In the APIC_IO case we might be granted IRQ 2, as this is typically
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* consumed by chaining between the two PIC components. If we're using
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* the APIC, however, this may not be the case, and as such we should
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* free the resource. (XXX untested)
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*
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* The generic ISA attachment code will handle allocating any other resources
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* that we don't explicitly claim here.
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*/
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static int
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atpic_attach(device_t dev)
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{
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#ifdef APIC_IO
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int rid;
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struct resource *res;
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/* try to allocate our IRQ and then free it */
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rid = 0;
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res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 0);
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if (res != NULL)
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bus_release_resource(dev, SYS_RES_IRQ, rid, res);
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#endif
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return(0);
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}
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static device_method_t atpic_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, atpic_probe),
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DEVMETHOD(device_attach, atpic_attach),
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DEVMETHOD(device_detach, bus_generic_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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{ 0, 0 }
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};
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static driver_t atpic_driver = {
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"atpic",
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atpic_methods,
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1, /* no softc */
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};
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static devclass_t atpic_devclass;
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DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
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DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
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/*
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* Handle a NMI, possibly a machine check.
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* return true to panic system, false to ignore.
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*/
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int
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isa_nmi(cd)
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int cd;
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{
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int retval = 0;
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#ifdef PC98
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int port = inb(0x33);
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log(LOG_CRIT, "NMI PC98 port = %x\n", port);
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if (epson_machine_id == 0x20)
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epson_outb(0xc16, epson_inb(0xc16) | 0x1);
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if (port & NMI_PARITY) {
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log(LOG_CRIT, "BASE RAM parity error, likely hardware failure.");
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retval = 1;
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} else if (port & NMI_EPARITY) {
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log(LOG_CRIT, "EXTENDED RAM parity error, likely hardware failure.");
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retval = 1;
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} else {
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log(LOG_CRIT, "\nNMI Resume ??\n");
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}
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#else /* IBM-PC */
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int isa_port = inb(0x61);
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int eisa_port = inb(0x461);
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log(LOG_CRIT, "NMI ISA %x, EISA %x\n", isa_port, eisa_port);
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#ifdef DEV_MCA
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if (MCA_system && mca_bus_nmi())
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return(0);
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#endif
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if (isa_port & NMI_PARITY) {
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log(LOG_CRIT, "RAM parity error, likely hardware failure.");
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retval = 1;
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}
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if (isa_port & NMI_IOCHAN) {
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log(LOG_CRIT, "I/O channel check, likely hardware failure.");
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retval = 1;
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}
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/*
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* On a real EISA machine, this will never happen. However it can
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* happen on ISA machines which implement XT style floating point
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* error handling (very rare). Save them from a meaningless panic.
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*/
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if (eisa_port == 0xff)
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return(retval);
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if (eisa_port & ENMI_WATCHDOG) {
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log(LOG_CRIT, "EISA watchdog timer expired, likely hardware failure.");
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retval = 1;
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}
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if (eisa_port & ENMI_BUSTIMER) {
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log(LOG_CRIT, "EISA bus timeout, likely hardware failure.");
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retval = 1;
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}
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if (eisa_port & ENMI_IOSTATUS) {
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log(LOG_CRIT, "EISA I/O port status error.");
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retval = 1;
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}
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#endif
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return(retval);
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}
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/*
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* ICU reinitialize when ICU configuration has lost.
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*/
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void icu_reinit()
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{
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int i;
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mtx_lock_spin(&icu_lock);
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init_i8259();
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for(i=0;i<ICU_LEN;i++)
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if(intr_handler[i] != isa_strayintr)
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INTREN(1<<i);
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mtx_unlock_spin(&icu_lock);
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}
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/*
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* Create a default interrupt table to avoid problems caused by
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* spurious interrupts during configuration of kernel, then setup
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* interrupt control unit.
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*/
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void
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isa_defaultirq()
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{
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int i;
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/* icu vectors */
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for (i = 0; i < ICU_LEN; i++)
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icu_unset(i, (driver_intr_t *)NULL);
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mtx_lock_spin(&icu_lock);
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init_i8259();
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mtx_unlock_spin(&icu_lock);
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}
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/*
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*initialize 8259's
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*/
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static void init_i8259()
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{
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#ifdef DEV_MCA
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if (MCA_system)
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outb(IO_ICU1, 0x19); /* reset; program device, four bytes */
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else
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#endif
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outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */
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outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */
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#ifdef PC98
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#ifdef AUTO_EOI_1
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outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */
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#else
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outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */
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#endif
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#else /* IBM-PC */
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#ifdef AUTO_EOI_1
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outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */
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#endif
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#endif /* PC98 */
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outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
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outb(IO_ICU1, 0x0a); /* default to IRR on read */
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#ifndef PC98
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outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
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#endif /* !PC98 */
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#ifdef DEV_MCA
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if (MCA_system)
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outb(IO_ICU2, 0x19); /* reset; program device, four bytes */
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else
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#endif
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outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */
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outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */
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#ifdef PC98
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outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */
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#else /* IBM-PC */
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#ifdef AUTO_EOI_2
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outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */
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#endif
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#endif /* PC98 */
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outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
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outb(IO_ICU2, 0x0a); /* default to IRR on read */
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}
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/*
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* Caught a stray interrupt, notify
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*/
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static void
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isa_strayintr(vcookiep)
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void *vcookiep;
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{
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int intr = (void **)vcookiep - &intr_unit[0];
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/*
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* XXX TODO print a different message for #7 if it is for a
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* glitch. Glitches can be distinguished from real #7's by
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* testing that the in-service bit is _not_ set. The test
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* must be done before sending an EOI so it can't be done if
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* we are using AUTO_EOI_1.
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*/
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if (intrcnt[1 + intr] <= 5)
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log(LOG_ERR, "stray irq %d\n", intr);
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if (intrcnt[1 + intr] == 5)
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log(LOG_CRIT,
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"too many stray irq %d's; not logging any more\n", intr);
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}
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#ifdef DEV_ISA
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/*
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* Return a bitmap of the current interrupt requests. This is 8259-specific
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* and is only suitable for use at probe time.
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*/
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intrmask_t
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isa_irq_pending()
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{
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u_char irr1;
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u_char irr2;
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mtx_lock_spin(&icu_lock);
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irr1 = inb(IO_ICU1);
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irr2 = inb(IO_ICU2);
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mtx_unlock_spin(&icu_lock);
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return ((irr2 << 8) | irr1);
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}
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#endif
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/*
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* Update intrnames array with the specified name. This is used by
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* vmstat(8) and the like.
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*/
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static void
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update_intrname(int intr, const char *name)
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{
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char buf[32];
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char *cp;
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int name_index, off, strayintr;
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/*
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* Initialise strings for bitbucket and stray interrupt counters.
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* These have statically allocated indices 0 and 1 through ICU_LEN.
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*/
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if (intrnames[0] == '\0') {
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off = sprintf(intrnames, "???") + 1;
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for (strayintr = 0; strayintr < ICU_LEN; strayintr++)
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off += sprintf(intrnames + off, "stray irq%d",
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strayintr) + 1;
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}
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if (name == NULL)
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name = "???";
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if (snprintf(buf, sizeof(buf), "%s irq%d", name, intr) >= sizeof(buf))
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goto use_bitbucket;
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/*
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* Search for `buf' in `intrnames'. In the usual case when it is
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* not found, append it to the end if there is enough space (the \0
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* terminator for the previous string, if any, becomes a separator).
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*/
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for (cp = intrnames, name_index = 0;
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cp != eintrnames && name_index < NR_INTRNAMES;
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cp += strlen(cp) + 1, name_index++) {
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if (*cp == '\0') {
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if (strlen(buf) >= eintrnames - cp)
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break;
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strcpy(cp, buf);
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goto found;
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}
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if (strcmp(cp, buf) == 0)
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goto found;
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}
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use_bitbucket:
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printf("update_intrname: counting %s irq%d as %s\n", name, intr,
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intrnames);
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name_index = 0;
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found:
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intr_countp[intr] = &intrcnt[name_index];
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}
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int
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icu_setup(int intr, driver_intr_t *handler, void *arg, int flags)
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{
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#ifdef FAST_HI
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int select; /* the select register is 8 bits */
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int vector;
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u_int32_t value; /* the window register is 32 bits */
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#endif /* FAST_HI */
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#if defined(APIC_IO)
|
|
if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */
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|
#else
|
|
if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID)
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|
#endif /* APIC_IO */
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|
return (EINVAL);
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|
#if 0
|
|
if (intr_handler[intr] != isa_strayintr)
|
|
return (EBUSY);
|
|
#endif
|
|
|
|
mtx_lock_spin(&icu_lock);
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|
intr_handler[intr] = handler;
|
|
intr_unit[intr] = arg;
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|
#ifdef FAST_HI
|
|
if (flags & INTR_FAST) {
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|
vector = TPR_FAST_INTS + intr;
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|
setidt(vector, fastintr[intr],
|
|
SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
|
|
}
|
|
else {
|
|
vector = TPR_SLOW_INTS + intr;
|
|
#ifdef APIC_INTR_REORDER
|
|
#ifdef APIC_INTR_HIGHPRI_CLOCK
|
|
/* XXX: Hack (kludge?) for more accurate clock. */
|
|
if (intr == apic_8254_intr || intr == 8) {
|
|
vector = TPR_FAST_INTS + intr;
|
|
}
|
|
#endif
|
|
#endif
|
|
setidt(vector, slowintr[intr],
|
|
SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
|
|
}
|
|
#ifdef APIC_INTR_REORDER
|
|
set_lapic_isrloc(intr, vector);
|
|
#endif
|
|
/*
|
|
* Reprogram the vector in the IO APIC.
|
|
*/
|
|
if (int_to_apicintpin[intr].ioapic >= 0) {
|
|
select = int_to_apicintpin[intr].redirindex;
|
|
value = io_apic_read(int_to_apicintpin[intr].ioapic,
|
|
select) & ~IOART_INTVEC;
|
|
io_apic_write(int_to_apicintpin[intr].ioapic,
|
|
select, value | vector);
|
|
}
|
|
#else
|
|
setidt(ICU_OFFSET + intr,
|
|
flags & INTR_FAST ? fastintr[intr] : slowintr[intr],
|
|
SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
|
|
#endif /* FAST_HI */
|
|
INTREN(1 << intr);
|
|
mtx_unlock_spin(&icu_lock);
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Dissociate an interrupt handler from an IRQ and set the handler to
|
|
* the stray interrupt handler. The 'handler' parameter is used only
|
|
* for consistency checking.
|
|
*/
|
|
int
|
|
icu_unset(intr, handler)
|
|
int intr;
|
|
driver_intr_t *handler;
|
|
{
|
|
|
|
if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr])
|
|
return (EINVAL);
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
INTRDIS(1 << intr);
|
|
intr_countp[intr] = &intrcnt[1 + intr];
|
|
intr_handler[intr] = isa_strayintr;
|
|
intr_unit[intr] = &intr_unit[intr];
|
|
#ifdef FAST_HI_XXX
|
|
/* XXX how do I re-create dvp here? */
|
|
setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr,
|
|
slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
|
|
#else /* FAST_HI */
|
|
#ifdef APIC_INTR_REORDER
|
|
set_lapic_isrloc(intr, ICU_OFFSET + intr);
|
|
#endif
|
|
setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL,
|
|
GSEL(GCODE_SEL, SEL_KPL));
|
|
#endif /* FAST_HI */
|
|
mtx_unlock_spin(&icu_lock);
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
ithds_init(void *dummy)
|
|
{
|
|
|
|
mtx_init(&ithds_table_lock, "ithread table lock", MTX_SPIN);
|
|
}
|
|
SYSINIT(ithds_init, SI_SUB_INTR, SI_ORDER_SECOND, ithds_init, NULL);
|
|
|
|
static void
|
|
ithread_enable(int vector)
|
|
{
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
INTREN(1 << vector);
|
|
mtx_unlock_spin(&icu_lock);
|
|
}
|
|
|
|
static void
|
|
ithread_disable(int vector)
|
|
{
|
|
|
|
mtx_lock_spin(&icu_lock);
|
|
INTRDIS(1 << vector);
|
|
mtx_unlock_spin(&icu_lock);
|
|
}
|
|
|
|
int
|
|
inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
|
|
enum intr_type flags, void **cookiep)
|
|
{
|
|
struct ithd *ithd; /* descriptor for the IRQ */
|
|
int errcode = 0;
|
|
int created_ithd = 0;
|
|
|
|
/*
|
|
* Work around a race where more than one CPU may be registering
|
|
* handlers on the same IRQ at the same time.
|
|
*/
|
|
mtx_lock_spin(&ithds_table_lock);
|
|
ithd = ithds[irq];
|
|
mtx_unlock_spin(&ithds_table_lock);
|
|
if (ithd == NULL) {
|
|
errcode = ithread_create(&ithd, irq, 0, ithread_disable,
|
|
ithread_enable, "irq%d:", irq);
|
|
if (errcode)
|
|
return (errcode);
|
|
mtx_lock_spin(&ithds_table_lock);
|
|
if (ithds[irq] == NULL) {
|
|
ithds[irq] = ithd;
|
|
created_ithd++;
|
|
mtx_unlock_spin(&ithds_table_lock);
|
|
} else {
|
|
struct ithd *orphan;
|
|
|
|
orphan = ithd;
|
|
ithd = ithds[irq];
|
|
mtx_unlock_spin(&ithds_table_lock);
|
|
ithread_destroy(orphan);
|
|
}
|
|
}
|
|
|
|
errcode = ithread_add_handler(ithd, name, handler, arg,
|
|
ithread_priority(flags), flags, cookiep);
|
|
|
|
if ((flags & INTR_FAST) == 0 || errcode)
|
|
/*
|
|
* The interrupt process must be in place, but
|
|
* not necessarily schedulable, before we
|
|
* initialize the ICU, since it may cause an
|
|
* immediate interrupt.
|
|
*/
|
|
if (icu_setup(irq, &sched_ithd, arg, flags) != 0)
|
|
panic("inthand_add: Can't initialize ICU");
|
|
|
|
if (errcode)
|
|
return (errcode);
|
|
|
|
if (flags & INTR_FAST) {
|
|
errcode = icu_setup(irq, handler, arg, flags);
|
|
if (errcode && bootverbose)
|
|
printf("\tinthand_add(irq%d) failed, result=%d\n",
|
|
irq, errcode);
|
|
if (errcode)
|
|
return (errcode);
|
|
}
|
|
|
|
update_intrname(irq, name);
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Deactivate and remove linked list the interrupt handler descriptor
|
|
* data connected created by an earlier call of inthand_add(), then
|
|
* adjust the interrupt masks if necessary.
|
|
*
|
|
* Return the memory held by the interrupt handler descriptor data
|
|
* structure to the system. First ensure the handler is not actively
|
|
* in use.
|
|
*/
|
|
int
|
|
inthand_remove(void *cookie)
|
|
{
|
|
|
|
return (ithread_remove_handler(cookie));
|
|
}
|