590adc1bc2
The block size is a property of the underlying hash algorithm, and has nothing to do with the HMAC construction. No functional change.
262 lines
6.8 KiB
C
262 lines
6.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2017 Conrad Meyer <cem@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#pragma once
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/*
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* Keccak SHAKE128 (if supported by the device?) uses a 1344 bit block.
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* SHA3-224 is the next largest block size, at 1152 bits. However, crypto(4)
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* doesn't support any SHA3 hash, so SHA2 is the constraint:
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*/
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#define CCP_HASH_MAX_BLOCK_SIZE (SHA2_512_BLOCK_LEN)
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#define CCP_AES_MAX_KEY_LEN (AES_XTS_MAX_KEY)
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#define CCP_MAX_CRYPTO_IV_LEN 32 /* GCM IV + GHASH context */
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#define MAX_HW_QUEUES 5
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#define MAX_LSB_REGIONS 8
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#ifndef __must_check
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#define __must_check __attribute__((__warn_unused_result__))
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#endif
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/*
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* Internal data structures.
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*/
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enum sha_version {
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SHA1,
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#if 0
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SHA2_224,
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#endif
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SHA2_256, SHA2_384, SHA2_512
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};
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struct ccp_session_hmac {
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struct auth_hash *auth_hash;
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int hash_len;
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unsigned int partial_digest_len;
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unsigned int auth_mode;
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unsigned int mk_size;
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char ipad[CCP_HASH_MAX_BLOCK_SIZE];
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char opad[CCP_HASH_MAX_BLOCK_SIZE];
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};
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struct ccp_session_gmac {
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int hash_len;
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char final_block[GMAC_BLOCK_LEN];
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};
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struct ccp_session_blkcipher {
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unsigned cipher_mode;
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unsigned cipher_type;
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unsigned key_len;
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unsigned iv_len;
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char enckey[CCP_AES_MAX_KEY_LEN];
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char iv[CCP_MAX_CRYPTO_IV_LEN];
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};
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struct ccp_session {
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bool active : 1;
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bool cipher_first : 1;
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int pending;
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enum { HMAC, BLKCIPHER, AUTHENC, GCM } mode;
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unsigned queue;
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union {
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struct ccp_session_hmac hmac;
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struct ccp_session_gmac gmac;
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};
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struct ccp_session_blkcipher blkcipher;
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};
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struct ccp_softc;
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struct ccp_queue {
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struct mtx cq_lock;
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unsigned cq_qindex;
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struct ccp_softc *cq_softc;
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/* Host memory and tracking structures for descriptor ring. */
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bus_dma_tag_t ring_desc_tag;
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bus_dmamap_t ring_desc_map;
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struct ccp_desc *desc_ring;
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bus_addr_t desc_ring_bus_addr;
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/* Callbacks and arguments ring; indices correspond to above ring. */
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struct ccp_completion_ctx *completions_ring;
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uint32_t qcontrol; /* Cached register value */
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unsigned lsb_mask; /* LSBs available to queue */
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int private_lsb; /* Reserved LSB #, or -1 */
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unsigned cq_head;
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unsigned cq_tail;
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unsigned cq_acq_tail;
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bool cq_waiting; /* Thread waiting for space */
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struct sglist *cq_sg_crp;
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struct sglist *cq_sg_ulptx;
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struct sglist *cq_sg_dst;
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};
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struct ccp_completion_ctx {
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void (*callback_fn)(struct ccp_queue *qp, struct ccp_session *s,
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void *arg, int error);
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void *callback_arg;
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struct ccp_session *session;
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};
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struct ccp_softc {
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device_t dev;
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int32_t cid;
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struct ccp_session *sessions;
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int nsessions;
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struct mtx lock;
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bool detaching;
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unsigned ring_size_order;
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/*
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* Each command queue is either public or private. "Private"
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* (PSP-only) by default. PSP grants access to some queues to host via
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* QMR (Queue Mask Register). Set bits are host accessible.
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*/
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uint8_t valid_queues;
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uint8_t hw_version;
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uint8_t num_queues;
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uint16_t hw_features;
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uint16_t num_lsb_entries;
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/* Primary BAR (RID 2) used for register access */
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bus_space_tag_t pci_bus_tag;
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bus_space_handle_t pci_bus_handle;
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int pci_resource_id;
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struct resource *pci_resource;
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/* Secondary BAR (RID 5) apparently used for MSI-X */
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int pci_resource_id_msix;
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struct resource *pci_resource_msix;
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/* Interrupt resources */
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void *intr_tag[2];
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struct resource *intr_res[2];
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unsigned intr_count;
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struct ccp_queue queues[MAX_HW_QUEUES];
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};
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/* Internal globals */
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SYSCTL_DECL(_hw_ccp);
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MALLOC_DECLARE(M_CCP);
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extern bool g_debug_print;
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extern struct ccp_softc *g_ccp_softc;
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/*
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* Debug macros.
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*/
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#define DPRINTF(dev, ...) do { \
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if (!g_debug_print) \
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break; \
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if ((dev) != NULL) \
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device_printf((dev), "XXX " __VA_ARGS__); \
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else \
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printf("ccpXXX: " __VA_ARGS__); \
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} while (0)
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#if 0
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#define INSECURE_DEBUG(dev, ...) do { \
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if (!g_debug_print) \
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break; \
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if ((dev) != NULL) \
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device_printf((dev), "XXX " __VA_ARGS__); \
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else \
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printf("ccpXXX: " __VA_ARGS__); \
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} while (0)
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#else
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#define INSECURE_DEBUG(dev, ...)
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#endif
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/*
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* Internal hardware manipulation routines.
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*/
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int ccp_hw_attach(device_t dev);
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void ccp_hw_detach(device_t dev);
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void ccp_queue_write_tail(struct ccp_queue *qp);
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#ifdef DDB
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void db_ccp_show_hw(struct ccp_softc *sc);
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void db_ccp_show_queue_hw(struct ccp_queue *qp);
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#endif
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/*
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* Internal hardware crypt-op submission routines.
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*/
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int ccp_authenc(struct ccp_queue *sc, struct ccp_session *s,
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struct cryptop *crp, struct cryptodesc *crda, struct cryptodesc *crde)
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__must_check;
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int ccp_blkcipher(struct ccp_queue *sc, struct ccp_session *s,
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struct cryptop *crp) __must_check;
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int ccp_gcm(struct ccp_queue *sc, struct ccp_session *s, struct cryptop *crp,
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struct cryptodesc *crda, struct cryptodesc *crde) __must_check;
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int ccp_hmac(struct ccp_queue *sc, struct ccp_session *s, struct cryptop *crp)
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__must_check;
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/*
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* Internal hardware TRNG read routine.
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*/
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u_int random_ccp_read(void *v, u_int c);
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/* XXX */
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int ccp_queue_acquire_reserve(struct ccp_queue *qp, unsigned n, int mflags)
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__must_check;
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void ccp_queue_abort(struct ccp_queue *qp);
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void ccp_queue_release(struct ccp_queue *qp);
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/*
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* Internal inline routines.
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*/
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static inline unsigned
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ccp_queue_get_active(struct ccp_queue *qp)
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{
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struct ccp_softc *sc;
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sc = qp->cq_softc;
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return ((qp->cq_tail - qp->cq_head) & ((1 << sc->ring_size_order) - 1));
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}
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static inline unsigned
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ccp_queue_get_ring_space(struct ccp_queue *qp)
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{
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struct ccp_softc *sc;
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sc = qp->cq_softc;
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return ((1 << sc->ring_size_order) - ccp_queue_get_active(qp) - 1);
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}
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