59ce78fef1
Tested at 100Mbit only, using Asus P4P800 onboard 3C940. The -stable version of this patch I have in use for ~2 weeks now, and works just fine for me. Based on: Nathan L. Binkert's patch for OpenBSD Patch submitted by and thanks to: Jung-uk Kim <jkim@niksun.com> MFC after: 2 weeks
315 lines
12 KiB
C
315 lines
12 KiB
C
/* $FreeBSD$ */
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/*
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* Principal Author: Parag Patel
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* Copyright (c) 2001
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Additonal Copyright (c) 2001 by Traakan Software under same licence.
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* Secondary Author: Matthew Jacob
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*/
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/*
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* Derived by information released by Intel under the following license:
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*
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* Copyright (c) 1999 - 2001, Intel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Marvell E1000 PHY registers
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*/
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#define E1000_MAX_REG_ADDRESS 0x1F
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#define E1000_CR 0x00 /* control register */
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#define E1000_CR_SPEED_SELECT_MSB 0x0040
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#define E1000_CR_COLL_TEST_ENABLE 0x0080
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#define E1000_CR_FULL_DUPLEX 0x0100
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#define E1000_CR_RESTART_AUTO_NEG 0x0200
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#define E1000_CR_ISOLATE 0x0400
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#define E1000_CR_POWER_DOWN 0x0800
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#define E1000_CR_AUTO_NEG_ENABLE 0x1000
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#define E1000_CR_SPEED_SELECT_LSB 0x2000
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#define E1000_CR_LOOPBACK 0x4000
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#define E1000_CR_RESET 0x8000
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#define E1000_CR_SPEED_1000 0x0040
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#define E1000_CR_SPEED_100 0x2000
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#define E1000_CR_SPEED_10 0x0000
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#define E1000_SR 0x01 /* status register */
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#define E1000_SR_EXTENDED 0x0001
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#define E1000_SR_JABBER_DETECT 0x0002
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#define E1000_SR_LINK_STATUS 0x0004
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#define E1000_SR_AUTO_NEG 0x0008
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#define E1000_SR_REMOTE_FAULT 0x0010
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#define E1000_SR_AUTO_NEG_COMPLETE 0x0020
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#define E1000_SR_PREAMBLE_SUPPRESS 0x0040
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#define E1000_SR_EXTENDED_STATUS 0x0100
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#define E1000_SR_100T2 0x0200
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#define E1000_SR_100T2_FD 0x0400
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#define E1000_SR_10T 0x0800
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#define E1000_SR_10T_FD 0x1000
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#define E1000_SR_100TX 0x2000
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#define E1000_SR_100TX_FD 0x4000
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#define E1000_SR_100T4 0x8000
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#define E1000_ID1 0x02 /* ID register 1 */
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#define E1000_ID2 0x03 /* ID register 2 */
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#define E1000_ID_88E1000 0x01410C50
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#define E1000_ID_88E1000S 0x01410C40
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#define E1000_ID_88E1011 0x01410C20
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#define E1000_ID_MASK 0xFFFFFFF0
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#define E1000_AR 0x04 /* autonegotiation advertise reg */
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#define E1000_AR_SELECTOR_FIELD 0x0001
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#define E1000_AR_10T 0x0020
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#define E1000_AR_10T_FD 0x0040
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#define E1000_AR_100TX 0x0080
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#define E1000_AR_100TX_FD 0x0100
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#define E1000_AR_100T4 0x0200
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#define E1000_AR_PAUSE 0x0400
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#define E1000_AR_ASM_DIR 0x0800
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#define E1000_AR_REMOTE_FAULT 0x2000
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#define E1000_AR_NEXT_PAGE 0x8000
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#define E1000_AR_SPEED_MASK 0x01E0
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/* Autonegotiation register bits for fiber cards (Alaska Only!) */
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#define E1000_FA_1000X_FD 0x0020
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#define E1000_FA_1000X 0x0040
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#define E1000_FA_SYM_PAUSE 0x0080
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#define E1000_FA_ASYM_PAUSE 0x0100
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#define E1000_FA_FAULT1 0x1000
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#define E1000_FA_FAULT2 0x2000
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#define E1000_FA_NEXT_PAGE 0x8000
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#define E1000_LPAR 0x05 /* autoneg link partner abilities reg */
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#define E1000_LPAR_SELECTOR_FIELD 0x0001
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#define E1000_LPAR_10T 0x0020
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#define E1000_LPAR_10T_FD 0x0040
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#define E1000_LPAR_100TX 0x0080
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#define E1000_LPAR_100TX_FD 0x0100
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#define E1000_LPAR_100T4 0x0200
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#define E1000_LPAR_PAUSE 0x0400
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#define E1000_LPAR_ASM_DIR 0x0800
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#define E1000_LPAR_REMOTE_FAULT 0x2000
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#define E1000_LPAR_ACKNOWLEDGE 0x4000
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#define E1000_LPAR_NEXT_PAGE 0x8000
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/* autoneg link partner ability register bits for fiber cards (Alaska Only!) */
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#define E1000_FPAR_1000X_FD 0x0020
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#define E1000_FPAR_1000X 0x0040
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#define E1000_FPAR_SYM_PAUSE 0x0080
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#define E1000_FPAR_ASYM_PAUSE 0x0100
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#define E1000_FPAR_FAULT1 0x1000
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#define E1000_FPAR_FAULT2 0x2000
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#define E1000_FPAR_ACK 0x4000
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#define E1000_FPAR_NEXT_PAGE 0x8000
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#define E1000_ER 0x06 /* autoneg expansion reg */
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#define E1000_ER_LP_NWAY 0x0001
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#define E1000_ER_PAGE_RXD 0x0002
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#define E1000_ER_NEXT_PAGE 0x0004
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#define E1000_ER_LP_NEXT_PAGE 0x0008
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#define E1000_ER_PAR_DETECT_FAULT 0x0100
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#define E1000_NPTX 0x07 /* autoneg next page TX */
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#define E1000_NPTX_MSG_CODE_FIELD 0x0001
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#define E1000_NPTX_TOGGLE 0x0800
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#define E1000_NPTX_ACKNOWLDGE2 0x1000
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#define E1000_NPTX_MSG_PAGE 0x2000
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#define E1000_NPTX_NEXT_PAGE 0x8000
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#define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */
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#define E1000_RNPR_MSG_CODE_FIELD 0x0001
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#define E1000_RNPR_TOGGLE 0x0800
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#define E1000_RNPR_ACKNOWLDGE2 0x1000
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#define E1000_RNPR_MSG_PAGE 0x2000
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#define E1000_RNPR_ACKNOWLDGE 0x4000
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#define E1000_RNPR_NEXT_PAGE 0x8000
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#define E1000_1GCR 0x09 /* 1000T (1G) control reg */
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#define E1000_1GCR_ASYM_PAUSE 0x0080
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#define E1000_1GCR_1000T 0x0100
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#define E1000_1GCR_1000T_FD 0x0200
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#define E1000_1GCR_REPEATER_DTE 0x0400
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#define E1000_1GCR_MS_VALUE 0x0800
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#define E1000_1GCR_MS_ENABLE 0x1000
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#define E1000_1GCR_TEST_MODE_NORMAL 0x0000
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#define E1000_1GCR_TEST_MODE_1 0x2000
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#define E1000_1GCR_TEST_MODE_2 0x4000
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#define E1000_1GCR_TEST_MODE_3 0x6000
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#define E1000_1GCR_TEST_MODE_4 0x8000
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#define E1000_1GCR_SPEED_MASK 0x0300
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#define E1000_1GSR 0x0A /* 1000T (1G) status reg */
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#define E1000_1GSR_IDLE_ERROR_CNT 0x0000
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#define E1000_1GSR_ASYM_PAUSE_DIR 0x0100
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#define E1000_1GSR_LP 0x0400
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#define E1000_1GSR_LP_FD 0x0800
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#define E1000_1GSR_REMOTE_RX_STATUS 0x1000
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#define E1000_1GSR_LOCAL_RX_STATUS 0x2000
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#define E1000_1GSR_MS_CONFIG_RES 0x4000
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#define E1000_1GSR_MS_CONFIG_FAULT 0x8000
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#define E1000_ESR 0x0F /* IEEE extended status reg */
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#define E1000_ESR_1000T 0x1000
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#define E1000_ESR_1000T_FD 0x2000
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#define E1000_ESR_1000X 0x4000
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#define E1000_ESR_1000X_FD 0x8000
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#define E1000_TX_POLARITY_MASK 0x0100
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#define E1000_TX_NORMAL_POLARITY 0
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#define E1000_AUTO_POLARITY_DISABLE 0x0010
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#define E1000_SCR 0x10 /* special control register */
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#define E1000_SCR_JABBER_DISABLE 0x0001
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#define E1000_SCR_POLARITY_REVERSAL 0x0002
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#define E1000_SCR_SQE_TEST 0x0004
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#define E1000_SCR_INT_FIFO_DISABLE 0x0008
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#define E1000_SCR_CLK125_DISABLE 0x0010
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#define E1000_SCR_MDI_MANUAL_MODE 0x0000
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#define E1000_SCR_MDIX_MANUAL_MODE 0x0020
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#define E1000_SCR_AUTO_X_1000T 0x0040
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#define E1000_SCR_AUTO_X_MODE 0x0060
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#define E1000_SCR_10BT_EXT_ENABLE 0x0080
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#define E1000_SCR_MII_5BIT_ENABLE 0x0100
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#define E1000_SCR_SCRAMBLER_DISABLE 0x0200
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#define E1000_SCR_FORCE_LINK_GOOD 0x0400
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#define E1000_SCR_ASSERT_CRS_ON_TX 0x0800
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#define E1000_SCR_RX_FIFO_DEPTH_6 0x0000
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#define E1000_SCR_RX_FIFO_DEPTH_8 0x1000
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#define E1000_SCR_RX_FIFO_DEPTH_10 0x2000
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#define E1000_SCR_RX_FIFO_DEPTH_12 0x3000
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#define E1000_SCR_TX_FIFO_DEPTH_6 0x0000
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#define E1000_SCR_TX_FIFO_DEPTH_8 0x4000
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#define E1000_SCR_TX_FIFO_DEPTH_10 0x8000
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#define E1000_SCR_TX_FIFO_DEPTH_12 0xC000
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#define E1000_SSR 0x11 /* special status register */
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#define E1000_SSR_JABBER 0x0001
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#define E1000_SSR_REV_POLARITY 0x0002
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#define E1000_SSR_MDIX 0x0020
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#define E1000_SSR_LINK 0x0400
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#define E1000_SSR_SPD_DPLX_RESOLVED 0x0800
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#define E1000_SSR_PAGE_RCVD 0x1000
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#define E1000_SSR_DUPLEX 0x2000
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#define E1000_SSR_SPEED 0xC000
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#define E1000_SSR_10MBS 0x0000
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#define E1000_SSR_100MBS 0x4000
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#define E1000_SSR_1000MBS 0x8000
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#define E1000_IER 0x12 /* interrupt enable reg */
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#define E1000_IER_JABBER 0x0001
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#define E1000_IER_POLARITY_CHANGE 0x0002
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#define E1000_IER_MDIX_CHANGE 0x0040
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#define E1000_IER_FIFO_OVER_UNDERUN 0x0080
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#define E1000_IER_FALSE_CARRIER 0x0100
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#define E1000_IER_SYMBOL_ERROR 0x0200
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#define E1000_IER_LINK_STAT_CHANGE 0x0400
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#define E1000_IER_AUTO_NEG_COMPLETE 0x0800
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#define E1000_IER_PAGE_RECEIVED 0x1000
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#define E1000_IER_DUPLEX_CHANGED 0x2000
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#define E1000_IER_SPEED_CHANGED 0x4000
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#define E1000_IER_AUTO_NEG_ERR 0x8000
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#define E1000_ISR 0x13 /* interrupt status reg */
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#define E1000_ISR_JABBER 0x0001
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#define E1000_ISR_POLARITY_CHANGE 0x0002
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#define E1000_ISR_MDIX_CHANGE 0x0040
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#define E1000_ISR_FIFO_OVER_UNDERUN 0x0080
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#define E1000_ISR_FALSE_CARRIER 0x0100
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#define E1000_ISR_SYMBOL_ERROR 0x0200
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#define E1000_ISR_LINK_STAT_CHANGE 0x0400
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#define E1000_ISR_AUTO_NEG_COMPLETE 0x0800
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#define E1000_ISR_PAGE_RECEIVED 0x1000
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#define E1000_ISR_DUPLEX_CHANGED 0x2000
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#define E1000_ISR_SPEED_CHANGED 0x4000
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#define E1000_ISR_AUTO_NEG_ERR 0x8000
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#define E1000_ESCR 0x14 /* extended special control reg */
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#define E1000_ESCR_FIBER_LOOPBACK 0x4000
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#define E1000_ESCR_DOWN_NO_IDLE 0x8000
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#define E1000_ESCR_TX_CLK_2_5 0x0060
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#define E1000_ESCR_TX_CLK_25 0x0070
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#define E1000_ESCR_TX_CLK_0 0x0000
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#define E1000_RECR 0x15 /* RX error counter reg */
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#define E1000_LCR 0x18 /* LED control reg */
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#define E1000_LCR_LED_TX 0x0001
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#define E1000_LCR_LED_RX 0x0002
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#define E1000_LCR_LED_DUPLEX 0x0004
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#define E1000_LCR_LINK 0x0008
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#define E1000_LCR_BLINK_42MS 0x0000
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#define E1000_LCR_BLINK_84MS 0x0100
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#define E1000_LCR_BLINK_170MS 0x0200
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#define E1000_LCR_BLINK_340MS 0x0300
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#define E1000_LCR_BLINK_670MS 0x0400
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#define E1000_LCR_PULSE_OFF 0x0000
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#define E1000_LCR_PULSE_21_42MS 0x1000
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#define E1000_LCR_PULSE_42_84MS 0x2000
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#define E1000_LCR_PULSE_84_170MS 0x3000
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#define E1000_LCR_PULSE_170_340MS 0x4000
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#define E1000_LCR_PULSE_340_670MS 0x5000
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#define E1000_LCR_PULSE_670_13S 0x6000
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#define E1000_LCR_PULSE_13_26S 0x7000
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/* The following register is found only on the 88E1011 Alaska PHY */
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#define E1000_ESSR 0x1B /* Extended PHY specific sts */
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#define E1000_ESSR_FIBER_LINK 0x2000
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#define E1000_ESSR_GMII_COPPER 0x000f
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#define E1000_ESSR_GMII_FIBER 0x0007
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#define E1000_ESSR_TBI_COPPER 0x000d
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#define E1000_ESSR_TBI_FIBER 0x0005
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