a47f39da1f
at least until I can root cause what's going on. The only platform I've seen this on is the AR9220 when attached to the AR71xx CPUs. I get immediate PCIe bus errors and all subsequent accesses cause further MIPS bus exceptions. I don't have any other big-endian platforms to test this on. If I get a chance (or two), I'll try to whack this on a bus analyser and see exactly what happens. I'd rather leave this on, especially for slower, embedded platforms. But the #ifdef hell is something I'm trying to avoid.
887 lines
27 KiB
C
887 lines
27 KiB
C
/*
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* Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#ifdef AH_SUPPORT_AR5312
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_devid.h"
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#include "ar5312/ar5312.h"
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#include "ar5312/ar5312reg.h"
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#include "ar5312/ar5312phy.h"
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#include "ah_eeprom_v3.h"
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/* Additional Time delay to wait after activiting the Base band */
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#define BASE_ACTIVATE_DELAY 100 /* 100 usec */
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#define PLL_SETTLE_DELAY 300 /* 300 usec */
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extern int16_t ar5212GetNf(struct ath_hal *, const struct ieee80211_channel *);
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extern void ar5212SetRateDurationTable(struct ath_hal *,
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const struct ieee80211_channel *);
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extern HAL_BOOL ar5212SetTransmitPower(struct ath_hal *ah,
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const struct ieee80211_channel *chan, uint16_t *rfXpdGain);
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extern void ar5212SetDeltaSlope(struct ath_hal *,
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const struct ieee80211_channel *);
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extern HAL_BOOL ar5212SetBoardValues(struct ath_hal *,
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const struct ieee80211_channel *);
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extern void ar5212SetIFSTiming(struct ath_hal *,
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const struct ieee80211_channel *);
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extern HAL_BOOL ar5212IsSpurChannel(struct ath_hal *,
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const struct ieee80211_channel *);
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extern HAL_BOOL ar5212ChannelChange(struct ath_hal *,
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const struct ieee80211_channel *);
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static HAL_BOOL ar5312SetResetReg(struct ath_hal *, uint32_t resetMask);
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static int
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write_common(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
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HAL_BOOL bChannelChange, int writes)
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{
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#define IS_NO_RESET_TIMER_ADDR(x) \
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( (((x) >= AR_BEACON) && ((x) <= AR_CFP_DUR)) || \
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(((x) >= AR_SLEEP1) && ((x) <= AR_SLEEP3)))
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#define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)]
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int i;
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/* Write Common Array Parameters */
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for (i = 0; i < ia->rows; i++) {
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uint32_t reg = V(i, 0);
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/* XXX timer/beacon setup registers? */
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/* On channel change, don't reset the PCU registers */
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if (!(bChannelChange && IS_NO_RESET_TIMER_ADDR(reg))) {
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OS_REG_WRITE(ah, reg, V(i, 1));
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DMA_YIELD(writes);
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}
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}
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return writes;
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#undef IS_NO_RESET_TIMER_ADDR
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#undef V
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}
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/*
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* Places the device in and out of reset and then places sane
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* values in the registers based on EEPROM config, initialization
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* vectors (as determined by the mode), and station configuration
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*
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* bChannelChange is used to preserve DMA/PCU registers across
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* a HW Reset during channel change.
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*/
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HAL_BOOL
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ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode,
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struct ieee80211_channel *chan,
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HAL_BOOL bChannelChange, HAL_STATUS *status)
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{
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#define N(a) (sizeof (a) / sizeof (a[0]))
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#define FAIL(_code) do { ecode = _code; goto bad; } while (0)
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struct ath_hal_5212 *ahp = AH5212(ah);
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HAL_CHANNEL_INTERNAL *ichan;
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const HAL_EEPROM *ee;
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uint32_t saveFrameSeqCount, saveDefAntenna;
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uint32_t macStaId1, synthDelay, txFrm2TxDStart;
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uint16_t rfXpdGain[MAX_NUM_PDGAINS_PER_CHANNEL];
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int16_t cckOfdmPwrDelta = 0;
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u_int modesIndex, freqIndex;
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HAL_STATUS ecode;
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int i, regWrites = 0;
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uint32_t testReg;
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uint32_t saveLedState = 0;
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HALASSERT(ah->ah_magic == AR5212_MAGIC);
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ee = AH_PRIVATE(ah)->ah_eeprom;
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OS_MARK(ah, AH_MARK_RESET, bChannelChange);
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/*
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* Map public channel to private.
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*/
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ichan = ath_hal_checkchannel(ah, chan);
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if (ichan == AH_NULL) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: invalid channel %u/0x%x; no mapping\n",
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__func__, chan->ic_freq, chan->ic_flags);
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FAIL(HAL_EINVAL);
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}
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switch (opmode) {
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case HAL_M_STA:
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case HAL_M_IBSS:
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case HAL_M_HOSTAP:
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case HAL_M_MONITOR:
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break;
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default:
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
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__func__, opmode);
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FAIL(HAL_EINVAL);
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break;
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}
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HALASSERT(ahp->ah_eeversion >= AR_EEPROM_VER3);
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/* Preserve certain DMA hardware registers on a channel change */
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if (bChannelChange) {
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/*
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* On Venice, the TSF is almost preserved across a reset;
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* it requires the doubling writes to the RESET_TSF
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* bit in the AR_BEACON register; it also has the quirk
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* of the TSF going back in time on the station (station
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* latches onto the last beacon's tsf during a reset 50%
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* of the times); the latter is not a problem for adhoc
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* stations since as long as the TSF is behind, it will
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* get resynchronized on receiving the next beacon; the
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* TSF going backwards in time could be a problem for the
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* sleep operation (supported on infrastructure stations
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* only) - the best and most general fix for this situation
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* is to resynchronize the various sleep/beacon timers on
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* the receipt of the next beacon i.e. when the TSF itself
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* gets resynchronized to the AP's TSF - power save is
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* needed to be temporarily disabled until that time
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*
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* Need to save the sequence number to restore it after
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* the reset!
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*/
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saveFrameSeqCount = OS_REG_READ(ah, AR_D_SEQNUM);
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} else
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saveFrameSeqCount = 0; /* NB: silence compiler */
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/* If the channel change is across the same mode - perform a fast channel change */
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if ((IS_2413(ah) || IS_5413(ah))) {
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/*
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* Channel change can only be used when:
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* -channel change requested - so it's not the initial reset.
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* -it's not a change to the current channel - often called when switching modes
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* on a channel
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* -the modes of the previous and requested channel are the same - some ugly code for XR
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*/
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if (bChannelChange &&
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AH_PRIVATE(ah)->ah_curchan != AH_NULL &&
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(chan->ic_freq != AH_PRIVATE(ah)->ah_curchan->ic_freq) &&
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((chan->ic_flags & IEEE80211_CHAN_ALLTURBO) ==
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(AH_PRIVATE(ah)->ah_curchan->ic_flags & IEEE80211_CHAN_ALLTURBO))) {
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if (ar5212ChannelChange(ah, chan))
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/* If ChannelChange completed - skip the rest of reset */
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return AH_TRUE;
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}
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}
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/*
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* Preserve the antenna on a channel change
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*/
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saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
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if (saveDefAntenna == 0) /* XXX magic constants */
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saveDefAntenna = 1;
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/* Save hardware flag before chip reset clears the register */
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macStaId1 = OS_REG_READ(ah, AR_STA_ID1) &
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(AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT);
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/* Save led state from pci config register */
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if (!IS_5315(ah))
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saveLedState = OS_REG_READ(ah, AR5312_PCICFG) &
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(AR_PCICFG_LEDCTL | AR_PCICFG_LEDMODE | AR_PCICFG_LEDBLINK |
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AR_PCICFG_LEDSLOW);
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ar5312RestoreClock(ah, opmode); /* move to refclk operation */
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/*
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* Adjust gain parameters before reset if
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* there's an outstanding gain updated.
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*/
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(void) ar5212GetRfgain(ah);
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if (!ar5312ChipReset(ah, chan)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
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FAIL(HAL_EIO);
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}
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/* Setup the indices for the next set of register array writes */
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if (IEEE80211_IS_CHAN_2GHZ(chan)) {
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freqIndex = 2;
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modesIndex = IEEE80211_IS_CHAN_108G(chan) ? 5 :
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IEEE80211_IS_CHAN_G(chan) ? 4 : 3;
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} else {
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freqIndex = 1;
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modesIndex = IEEE80211_IS_CHAN_ST(chan) ? 2 : 1;
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}
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OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
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/* Set correct Baseband to analog shift setting to access analog chips. */
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OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
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regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);
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regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,
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regWrites);
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ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
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OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
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if (IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))
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ar5212SetIFSTiming(ah, chan);
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/* Overwrite INI values for revised chipsets */
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if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) {
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/* ADC_CTL */
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OS_REG_WRITE(ah, AR_PHY_ADC_CTL,
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SM(2, AR_PHY_ADC_CTL_OFF_INBUFGAIN) |
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SM(2, AR_PHY_ADC_CTL_ON_INBUFGAIN) |
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AR_PHY_ADC_CTL_OFF_PWDDAC |
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AR_PHY_ADC_CTL_OFF_PWDADC);
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/* TX_PWR_ADJ */
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if (chan->channel == 2484) {
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cckOfdmPwrDelta = SCALE_OC_DELTA(ee->ee_cckOfdmPwrDelta - ee->ee_scaledCh14FilterCckDelta);
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} else {
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cckOfdmPwrDelta = SCALE_OC_DELTA(ee->ee_cckOfdmPwrDelta);
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}
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if (IEEE80211_IS_CHAN_G(chan)) {
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OS_REG_WRITE(ah, AR_PHY_TXPWRADJ,
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SM((ee->ee_cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_GAIN_DELTA) |
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SM((cckOfdmPwrDelta*-1), AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX));
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} else {
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OS_REG_WRITE(ah, AR_PHY_TXPWRADJ, 0);
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}
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/* Add barker RSSI thresh enable as disabled */
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OS_REG_CLR_BIT(ah, AR_PHY_DAG_CTRLCCK,
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AR_PHY_DAG_CTRLCCK_EN_RSSI_THR);
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OS_REG_RMW_FIELD(ah, AR_PHY_DAG_CTRLCCK,
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AR_PHY_DAG_CTRLCCK_RSSI_THR, 2);
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/* Set the mute mask to the correct default */
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OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F);
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}
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if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) {
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/* Clear reg to alllow RX_CLEAR line debug */
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OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0);
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}
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if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) {
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#ifdef notyet
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/* Enable burst prefetch for the data queues */
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OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... );
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/* Enable double-buffering */
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OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS);
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#endif
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}
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if (IS_5312_2_X(ah)) {
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/* ADC_CTRL */
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OS_REG_WRITE(ah, AR_PHY_SIGMA_DELTA,
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SM(2, AR_PHY_SIGMA_DELTA_ADC_SEL) |
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SM(4, AR_PHY_SIGMA_DELTA_FILT2) |
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SM(0x16, AR_PHY_SIGMA_DELTA_FILT1) |
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SM(0, AR_PHY_SIGMA_DELTA_ADC_CLIP));
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if (IEEE80211_IS_CHAN_2GHZ(chan))
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OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN, AR_PHY_RXGAIN_TXRX_RF_MAX, 0x0F);
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/* CCK Short parameter adjustment in 11B mode */
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if (IEEE80211_IS_CHAN_B(chan))
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OS_REG_RMW_FIELD(ah, AR_PHY_CCK_RXCTRL4, AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT, 12);
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/* Set ADC/DAC select values */
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OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x04);
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/* Increase 11A AGC Settling */
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if (IEEE80211_IS_CHAN_A(chan))
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OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_AGC, 32);
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} else {
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/* Set ADC/DAC select values */
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OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
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}
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/* Setup the transmit power values. */
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if (!ar5212SetTransmitPower(ah, chan, rfXpdGain)) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: error init'ing transmit power\n", __func__);
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FAIL(HAL_EIO);
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}
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/* Write the analog registers */
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if (!ahp->ah_rfHal->setRfRegs(ah, chan, modesIndex, rfXpdGain)) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5212SetRfRegs failed\n",
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__func__);
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FAIL(HAL_EIO);
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}
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/* Write delta slope for OFDM enabled modes (A, G, Turbo) */
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if (IEEE80211_IS_CHAN_OFDM(chan)) {
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if (IS_5413(ah) ||
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AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3)
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ar5212SetSpurMitigation(ah, chan);
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ar5212SetDeltaSlope(ah, chan);
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}
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/* Setup board specific options for EEPROM version 3 */
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if (!ar5212SetBoardValues(ah, chan)) {
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HALDEBUG(ah, HAL_DEBUG_ANY,
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"%s: error setting board options\n", __func__);
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FAIL(HAL_EIO);
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}
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/* Restore certain DMA hardware registers on a channel change */
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if (bChannelChange)
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OS_REG_WRITE(ah, AR_D_SEQNUM, saveFrameSeqCount);
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OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
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OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
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OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
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| macStaId1
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| AR_STA_ID1_RTS_USE_DEF
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| ahp->ah_staId1Defaults
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);
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ar5212SetOperatingMode(ah, opmode);
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/* Set Venice BSSID mask according to current state */
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OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
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OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
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/* Restore previous led state */
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if (!IS_5315(ah))
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OS_REG_WRITE(ah, AR5312_PCICFG, OS_REG_READ(ah, AR_PCICFG) | saveLedState);
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/* Restore previous antenna */
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OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
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/* then our BSSID */
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OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
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OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
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/* Restore bmiss rssi & count thresholds */
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OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
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OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
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if (!ar5212SetChannel(ah, chan))
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FAIL(HAL_EIO);
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OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
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ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1);
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ar5212SetRateDurationTable(ah, chan);
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/* Set Tx frame start to tx data start delay */
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if (IS_RAD5112_ANY(ah) &&
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(IEEE80211_IS_CHAN_HALF(chan) || IEEE80211_IS_CHAN_QUARTER(chan))) {
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txFrm2TxDStart =
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IEEE80211_IS_CHAN_HALF(chan) ?
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TX_FRAME_D_START_HALF_RATE:
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TX_FRAME_D_START_QUARTER_RATE;
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OS_REG_RMW_FIELD(ah, AR_PHY_TX_CTL,
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AR_PHY_TX_FRAME_TO_TX_DATA_START, txFrm2TxDStart);
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}
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/*
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* Setup fast diversity.
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* Fast diversity can be enabled or disabled via regadd.txt.
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* Default is enabled.
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* For reference,
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* Disable: reg val
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* 0x00009860 0x00009d18 (if 11a / 11g, else no change)
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* 0x00009970 0x192bb514
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* 0x0000a208 0xd03e4648
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*
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* Enable: 0x00009860 0x00009d10 (if 11a / 11g, else no change)
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* 0x00009970 0x192fb514
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* 0x0000a208 0xd03e6788
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*/
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/* XXX Setup pre PHY ENABLE EAR additions */
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/* flush SCAL reg */
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if (IS_5312_2_X(ah)) {
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(void) OS_REG_READ(ah, AR_PHY_SLEEP_SCAL);
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}
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/*
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* Wait for the frequency synth to settle (synth goes on
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* via AR_PHY_ACTIVE_EN). Read the phy active delay register.
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* Value is in 100ns increments.
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*/
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synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
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if (IEEE80211_IS_CHAN_B(chan)) {
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synthDelay = (4 * synthDelay) / 22;
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} else {
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synthDelay /= 10;
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}
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/* Activate the PHY (includes baseband activate and synthesizer on) */
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OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
|
|
|
|
/*
|
|
* There is an issue if the AP starts the calibration before
|
|
* the base band timeout completes. This could result in the
|
|
* rx_clear false triggering. As a workaround we add delay an
|
|
* extra BASE_ACTIVATE_DELAY usecs to ensure this condition
|
|
* does not happen.
|
|
*/
|
|
if (IEEE80211_IS_CHAN_HALF(chan)) {
|
|
OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY);
|
|
} else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
|
|
OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY);
|
|
} else {
|
|
OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY);
|
|
}
|
|
|
|
/*
|
|
* The udelay method is not reliable with notebooks.
|
|
* Need to check to see if the baseband is ready
|
|
*/
|
|
testReg = OS_REG_READ(ah, AR_PHY_TESTCTRL);
|
|
/* Selects the Tx hold */
|
|
OS_REG_WRITE(ah, AR_PHY_TESTCTRL, AR_PHY_TESTCTRL_TXHOLD);
|
|
i = 0;
|
|
while ((i++ < 20) &&
|
|
(OS_REG_READ(ah, 0x9c24) & 0x10)) /* test if baseband not ready */ OS_DELAY(200);
|
|
OS_REG_WRITE(ah, AR_PHY_TESTCTRL, testReg);
|
|
|
|
/* Calibrate the AGC and start a NF calculation */
|
|
OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
|
|
OS_REG_READ(ah, AR_PHY_AGC_CONTROL)
|
|
| AR_PHY_AGC_CONTROL_CAL
|
|
| AR_PHY_AGC_CONTROL_NF);
|
|
|
|
if (!IEEE80211_IS_CHAN_B(chan) && ahp->ah_bIQCalibration != IQ_CAL_DONE) {
|
|
/* Start IQ calibration w/ 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples */
|
|
OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4,
|
|
AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
|
|
INIT_IQCAL_LOG_COUNT_MAX);
|
|
OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4,
|
|
AR_PHY_TIMING_CTRL4_DO_IQCAL);
|
|
ahp->ah_bIQCalibration = IQ_CAL_RUNNING;
|
|
} else
|
|
ahp->ah_bIQCalibration = IQ_CAL_INACTIVE;
|
|
|
|
/* Setup compression registers */
|
|
ar5212SetCompRegs(ah);
|
|
|
|
/* Set 1:1 QCU to DCU mapping for all queues */
|
|
for (i = 0; i < AR_NUM_DCU; i++)
|
|
OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
|
|
|
|
ahp->ah_intrTxqs = 0;
|
|
for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++)
|
|
ar5212ResetTxQueue(ah, i);
|
|
|
|
/*
|
|
* Setup interrupt handling. Note that ar5212ResetTxQueue
|
|
* manipulates the secondary IMR's as queues are enabled
|
|
* and disabled. This is done with RMW ops to insure the
|
|
* settings we make here are preserved.
|
|
*/
|
|
ahp->ah_maskReg = AR_IMR_TXOK | AR_IMR_TXERR | AR_IMR_TXURN
|
|
| AR_IMR_RXOK | AR_IMR_RXERR | AR_IMR_RXORN
|
|
| AR_IMR_HIUERR
|
|
;
|
|
if (opmode == HAL_M_HOSTAP)
|
|
ahp->ah_maskReg |= AR_IMR_MIB;
|
|
OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
|
|
/* Enable bus errors that are OR'd to set the HIUERR bit */
|
|
OS_REG_WRITE(ah, AR_IMR_S2,
|
|
OS_REG_READ(ah, AR_IMR_S2)
|
|
| AR_IMR_S2_MCABT | AR_IMR_S2_SSERR | AR_IMR_S2_DPERR);
|
|
|
|
if (AH_PRIVATE(ah)->ah_rfkillEnabled)
|
|
ar5212EnableRfKill(ah);
|
|
|
|
if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
|
|
HALDEBUG(ah, HAL_DEBUG_ANY,
|
|
"%s: offset calibration failed to complete in 1ms;"
|
|
" noisy environment?\n", __func__);
|
|
}
|
|
|
|
/*
|
|
* Set clocks back to 32kHz if they had been using refClk, then
|
|
* use an external 32kHz crystal when sleeping, if one exists.
|
|
*/
|
|
ar5312SetupClock(ah, opmode);
|
|
|
|
/*
|
|
* Writing to AR_BEACON will start timers. Hence it should
|
|
* be the last register to be written. Do not reset tsf, do
|
|
* not enable beacons at this point, but preserve other values
|
|
* like beaconInterval.
|
|
*/
|
|
OS_REG_WRITE(ah, AR_BEACON,
|
|
(OS_REG_READ(ah, AR_BEACON) &~ (AR_BEACON_EN | AR_BEACON_RESET_TSF)));
|
|
|
|
/* XXX Setup post reset EAR additions */
|
|
|
|
/* QoS support */
|
|
if (AH_PRIVATE(ah)->ah_macVersion > AR_SREV_VERSION_VENICE ||
|
|
(AH_PRIVATE(ah)->ah_macVersion == AR_SREV_VERSION_VENICE &&
|
|
AH_PRIVATE(ah)->ah_macRev >= AR_SREV_GRIFFIN_LITE)) {
|
|
OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */
|
|
OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */
|
|
}
|
|
|
|
/* Turn on NOACK Support for QoS packets */
|
|
OS_REG_WRITE(ah, AR_NOACK,
|
|
SM(2, AR_NOACK_2BIT_VALUE) |
|
|
SM(5, AR_NOACK_BIT_OFFSET) |
|
|
SM(0, AR_NOACK_BYTE_OFFSET));
|
|
|
|
/* Restore user-specified settings */
|
|
if (ahp->ah_miscMode != 0)
|
|
OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
|
|
if (ahp->ah_slottime != (u_int) -1)
|
|
ar5212SetSlotTime(ah, ahp->ah_slottime);
|
|
if (ahp->ah_acktimeout != (u_int) -1)
|
|
ar5212SetAckTimeout(ah, ahp->ah_acktimeout);
|
|
if (ahp->ah_ctstimeout != (u_int) -1)
|
|
ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout);
|
|
if (ahp->ah_sifstime != (u_int) -1)
|
|
ar5212SetSifsTime(ah, ahp->ah_sifstime);
|
|
if (AH_PRIVATE(ah)->ah_diagreg != 0)
|
|
OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
|
|
|
|
AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
|
|
|
|
if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
|
|
chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
|
|
|
|
HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
|
|
|
|
OS_MARK(ah, AH_MARK_RESET_DONE, 0);
|
|
|
|
return AH_TRUE;
|
|
bad:
|
|
OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
|
|
if (status != AH_NULL)
|
|
*status = ecode;
|
|
return AH_FALSE;
|
|
#undef FAIL
|
|
#undef N
|
|
}
|
|
|
|
/*
|
|
* Places the PHY and Radio chips into reset. A full reset
|
|
* must be called to leave this state. The PCI/MAC/PCU are
|
|
* not placed into reset as we must receive interrupt to
|
|
* re-enable the hardware.
|
|
*/
|
|
HAL_BOOL
|
|
ar5312PhyDisable(struct ath_hal *ah)
|
|
{
|
|
return ar5312SetResetReg(ah, AR_RC_BB);
|
|
}
|
|
|
|
/*
|
|
* Places all of hardware into reset
|
|
*/
|
|
HAL_BOOL
|
|
ar5312Disable(struct ath_hal *ah)
|
|
{
|
|
if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
|
|
return AH_FALSE;
|
|
/*
|
|
* Reset the HW - PCI must be reset after the rest of the
|
|
* device has been reset.
|
|
*/
|
|
return ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB);
|
|
}
|
|
|
|
/*
|
|
* Places the hardware into reset and then pulls it out of reset
|
|
*
|
|
* TODO: Only write the PLL if we're changing to or from CCK mode
|
|
*
|
|
* WARNING: The order of the PLL and mode registers must be correct.
|
|
*/
|
|
HAL_BOOL
|
|
ar5312ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan)
|
|
{
|
|
|
|
OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);
|
|
|
|
/*
|
|
* Reset the HW
|
|
*/
|
|
if (!ar5312SetResetReg(ah, AR_RC_MAC | AR_RC_BB)) {
|
|
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",
|
|
__func__);
|
|
return AH_FALSE;
|
|
}
|
|
|
|
/* Bring out of sleep mode (AGAIN) */
|
|
if (!ar5312SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
|
|
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetPowerMode failed\n",
|
|
__func__);
|
|
return AH_FALSE;
|
|
}
|
|
|
|
/* Clear warm reset register */
|
|
if (!ar5312SetResetReg(ah, 0)) {
|
|
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: ar5312SetResetReg failed\n",
|
|
__func__);
|
|
return AH_FALSE;
|
|
}
|
|
|
|
/*
|
|
* Perform warm reset before the mode/PLL/turbo registers
|
|
* are changed in order to deactivate the radio. Mode changes
|
|
* with an active radio can result in corrupted shifts to the
|
|
* radio device.
|
|
*/
|
|
|
|
/*
|
|
* Set CCK and Turbo modes correctly.
|
|
*/
|
|
if (chan != AH_NULL) { /* NB: can be null during attach */
|
|
uint32_t rfMode, phyPLL = 0, curPhyPLL, turbo;
|
|
|
|
if (IS_RAD5112_ANY(ah)) {
|
|
rfMode = AR_PHY_MODE_AR5112;
|
|
if (!IS_5315(ah)) {
|
|
if (IEEE80211_IS_CHAN_CCK(chan)) {
|
|
phyPLL = AR_PHY_PLL_CTL_44_5312;
|
|
} else {
|
|
if (IEEE80211_IS_CHAN_HALF(chan)) {
|
|
phyPLL = AR_PHY_PLL_CTL_40_5312_HALF;
|
|
} else if (IEEE80211_IS_CHAN_QUARTER(chan)) {
|
|
phyPLL = AR_PHY_PLL_CTL_40_5312_QUARTER;
|
|
} else {
|
|
phyPLL = AR_PHY_PLL_CTL_40_5312;
|
|
}
|
|
}
|
|
} else {
|
|
if (IEEE80211_IS_CHAN_CCK(chan))
|
|
phyPLL = AR_PHY_PLL_CTL_44_5112;
|
|
else
|
|
phyPLL = AR_PHY_PLL_CTL_40_5112;
|
|
if (IEEE80211_IS_CHAN_HALF(chan))
|
|
phyPLL |= AR_PHY_PLL_CTL_HALF;
|
|
else if (IEEE80211_IS_CHAN_QUARTER(chan))
|
|
phyPLL |= AR_PHY_PLL_CTL_QUARTER;
|
|
}
|
|
} else {
|
|
rfMode = AR_PHY_MODE_AR5111;
|
|
if (IEEE80211_IS_CHAN_CCK(chan))
|
|
phyPLL = AR_PHY_PLL_CTL_44;
|
|
else
|
|
phyPLL = AR_PHY_PLL_CTL_40;
|
|
if (IEEE80211_IS_CHAN_HALF(chan))
|
|
phyPLL = AR_PHY_PLL_CTL_HALF;
|
|
else if (IEEE80211_IS_CHAN_QUARTER(chan))
|
|
phyPLL = AR_PHY_PLL_CTL_QUARTER;
|
|
}
|
|
if (IEEE80211_IS_CHAN_G(chan))
|
|
rfMode |= AR_PHY_MODE_DYNAMIC;
|
|
else if (IEEE80211_IS_CHAN_OFDM(chan))
|
|
rfMode |= AR_PHY_MODE_OFDM;
|
|
else
|
|
rfMode |= AR_PHY_MODE_CCK;
|
|
if (IEEE80211_IS_CHAN_5GHZ(chan))
|
|
rfMode |= AR_PHY_MODE_RF5GHZ;
|
|
else
|
|
rfMode |= AR_PHY_MODE_RF2GHZ;
|
|
turbo = IEEE80211_IS_CHAN_TURBO(chan) ?
|
|
(AR_PHY_FC_TURBO_MODE | AR_PHY_FC_TURBO_SHORT) : 0;
|
|
curPhyPLL = OS_REG_READ(ah, AR_PHY_PLL_CTL);
|
|
/*
|
|
* PLL, Mode, and Turbo values must be written in the correct
|
|
* order to ensure:
|
|
* - The PLL cannot be set to 44 unless the CCK or DYNAMIC
|
|
* mode bit is set
|
|
* - Turbo cannot be set at the same time as CCK or DYNAMIC
|
|
*/
|
|
if (IEEE80211_IS_CHAN_CCK(chan)) {
|
|
OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
|
|
OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
|
|
if (curPhyPLL != phyPLL) {
|
|
OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL);
|
|
/* Wait for the PLL to settle */
|
|
OS_DELAY(PLL_SETTLE_DELAY);
|
|
}
|
|
} else {
|
|
if (curPhyPLL != phyPLL) {
|
|
OS_REG_WRITE(ah, AR_PHY_PLL_CTL, phyPLL);
|
|
/* Wait for the PLL to settle */
|
|
OS_DELAY(PLL_SETTLE_DELAY);
|
|
}
|
|
OS_REG_WRITE(ah, AR_PHY_TURBO, turbo);
|
|
OS_REG_WRITE(ah, AR_PHY_MODE, rfMode);
|
|
}
|
|
}
|
|
return AH_TRUE;
|
|
}
|
|
|
|
/*
|
|
* Write the given reset bit mask into the reset register
|
|
*/
|
|
static HAL_BOOL
|
|
ar5312SetResetReg(struct ath_hal *ah, uint32_t resetMask)
|
|
{
|
|
uint32_t mask = resetMask ? resetMask : ~0;
|
|
HAL_BOOL rt;
|
|
|
|
if ((rt = ar5312MacReset(ah, mask)) == AH_FALSE) {
|
|
return rt;
|
|
}
|
|
if ((resetMask & AR_RC_MAC) == 0) {
|
|
if (isBigEndian()) {
|
|
/*
|
|
* Set CFG, little-endian for descriptor accesses.
|
|
*/
|
|
#ifdef AH_NEED_DESC_SWAP
|
|
mask = INIT_CONFIG_STATUS | AR_CFG_SWRD;
|
|
#else
|
|
mask = INIT_CONFIG_STATUS |
|
|
AR_CFG_SWTD | AR_CFG_SWRD;
|
|
#endif
|
|
OS_REG_WRITE(ah, AR_CFG, mask);
|
|
} else
|
|
OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
|
|
}
|
|
return rt;
|
|
}
|
|
|
|
/*
|
|
* ar5312MacReset resets (and then un-resets) the specified
|
|
* wireless components.
|
|
* Note: The RCMask cannot be zero on entering from ar5312SetResetReg.
|
|
*/
|
|
|
|
HAL_BOOL
|
|
ar5312MacReset(struct ath_hal *ah, unsigned int RCMask)
|
|
{
|
|
int wlanNum = AR5312_UNIT(ah);
|
|
uint32_t resetBB, resetBits, regMask;
|
|
uint32_t reg;
|
|
|
|
if (RCMask == 0)
|
|
return(AH_FALSE);
|
|
#if ( AH_SUPPORT_2316 || AH_SUPPORT_2317 )
|
|
if (IS_5315(ah)) {
|
|
switch(wlanNum) {
|
|
case 0:
|
|
resetBB = AR5315_RC_BB0_CRES | AR5315_RC_WBB0_RES;
|
|
/* Warm and cold reset bits for wbb */
|
|
resetBits = AR5315_RC_WMAC0_RES;
|
|
break;
|
|
case 1:
|
|
resetBB = AR5315_RC_BB1_CRES | AR5315_RC_WBB1_RES;
|
|
/* Warm and cold reset bits for wbb */
|
|
resetBits = AR5315_RC_WMAC1_RES;
|
|
break;
|
|
default:
|
|
return(AH_FALSE);
|
|
}
|
|
regMask = ~(resetBB | resetBits);
|
|
|
|
/* read before */
|
|
reg = OS_REG_READ(ah,
|
|
(AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5315_RESET));
|
|
|
|
if (RCMask == AR_RC_BB) {
|
|
/* Put baseband in reset */
|
|
reg |= resetBB; /* Cold and warm reset the baseband bits */
|
|
} else {
|
|
/*
|
|
* Reset the MAC and baseband. This is a bit different than
|
|
* the PCI version, but holding in reset causes problems.
|
|
*/
|
|
reg &= regMask;
|
|
reg |= (resetBits | resetBB) ;
|
|
}
|
|
OS_REG_WRITE(ah,
|
|
(AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET),
|
|
reg);
|
|
/* read after */
|
|
OS_REG_READ(ah,
|
|
(AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5315_RESET));
|
|
OS_DELAY(100);
|
|
|
|
/* Bring MAC and baseband out of reset */
|
|
reg &= regMask;
|
|
/* read before */
|
|
OS_REG_READ(ah,
|
|
(AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));
|
|
OS_REG_WRITE(ah,
|
|
(AR5315_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5315_RESET),
|
|
reg);
|
|
/* read after */
|
|
OS_REG_READ(ah,
|
|
(AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET));
|
|
|
|
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
|
|
switch(wlanNum) {
|
|
case 0:
|
|
resetBB = AR5312_RC_BB0_CRES | AR5312_RC_WBB0_RES;
|
|
/* Warm and cold reset bits for wbb */
|
|
resetBits = AR5312_RC_WMAC0_RES;
|
|
break;
|
|
case 1:
|
|
resetBB = AR5312_RC_BB1_CRES | AR5312_RC_WBB1_RES;
|
|
/* Warm and cold reset bits for wbb */
|
|
resetBits = AR5312_RC_WMAC1_RES;
|
|
break;
|
|
default:
|
|
return(AH_FALSE);
|
|
}
|
|
regMask = ~(resetBB | resetBits);
|
|
|
|
/* read before */
|
|
reg = OS_REG_READ(ah,
|
|
(AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) + AR5312_RESET));
|
|
|
|
if (RCMask == AR_RC_BB) {
|
|
/* Put baseband in reset */
|
|
reg |= resetBB; /* Cold and warm reset the baseband bits */
|
|
} else {
|
|
/*
|
|
* Reset the MAC and baseband. This is a bit different than
|
|
* the PCI version, but holding in reset causes problems.
|
|
*/
|
|
reg &= regMask;
|
|
reg |= (resetBits | resetBB) ;
|
|
}
|
|
OS_REG_WRITE(ah,
|
|
(AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET),
|
|
reg);
|
|
/* read after */
|
|
OS_REG_READ(ah,
|
|
(AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh) +AR5312_RESET));
|
|
OS_DELAY(100);
|
|
|
|
/* Bring MAC and baseband out of reset */
|
|
reg &= regMask;
|
|
/* read before */
|
|
OS_REG_READ(ah,
|
|
(AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET));
|
|
OS_REG_WRITE(ah,
|
|
(AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh)+AR5312_RESET),
|
|
reg);
|
|
/* read after */
|
|
OS_REG_READ(ah,
|
|
(AR5312_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5312_RESET));
|
|
}
|
|
return(AH_TRUE);
|
|
}
|
|
|
|
#endif /* AH_SUPPORT_AR5312 */
|