438 lines
9.2 KiB
C
438 lines
9.2 KiB
C
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD
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* $FreeBSD$
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*/
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#ifndef __NLM_HAL_MMIO_H__
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#define __NLM_HAL_MMIO_H__
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/*
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* This file contains platform specific memory mapped IO implementation
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* and will provide a way to read 32/64 bit memory mapped registers in
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* all ABIs
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*/
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/*
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* For o32 compilation, we have to disable interrupts and enable KX bit to
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* access 64 bit addresses or data.
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*
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* We need to disable interrupts because we save just the lower 32 bits of
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* registers in interrupt handling. So if we get hit by an interrupt while
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* using the upper 32 bits of a register, we lose.
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*/
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static inline uint32_t nlm_save_flags_kx(void)
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{
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uint32_t sr = mips_rd_status();
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mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_KX);
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return (sr);
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}
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static inline uint32_t nlm_save_flags_cop2(void)
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{
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uint32_t sr = mips_rd_status();
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mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_COP_2_BIT);
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return (sr);
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}
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static inline void nlm_restore_flags(uint32_t sr)
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{
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mips_wr_status(sr);
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}
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static inline uint32_t
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nlm_load_word(uint64_t addr)
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{
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volatile uint32_t *p = (volatile uint32_t *)(long)addr;
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return *p;
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}
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static inline void
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nlm_store_word(uint64_t addr, uint32_t val)
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{
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volatile uint32_t *p = (volatile uint32_t *)(long)addr;
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*p = val;
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}
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#if defined(__mips_n64) || defined(__mips_n32)
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static inline uint64_t
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nlm_load_dword(volatile uint64_t addr)
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{
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volatile uint64_t *p = (volatile uint64_t *)(long)addr;
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return *p;
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}
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static inline void
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nlm_store_dword(volatile uint64_t addr, uint64_t val)
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{
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volatile uint64_t *p = (volatile uint64_t *)(long)addr;
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*p = val;
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}
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#else /* o32 */
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static inline uint64_t
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nlm_load_dword(uint64_t addr)
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{
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volatile uint64_t *p = (volatile uint64_t *)(long)addr;
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uint32_t valhi, vallo, sr;
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sr = nlm_save_flags_kx();
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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"ld $8, 0(%2)\n\t"
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"dsra32 %0, $8, 0\n\t"
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"sll %1, $8, 0\n\t"
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".set pop\n"
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: "=r"(valhi), "=r"(vallo)
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: "r"(p)
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: "$8");
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nlm_restore_flags(sr);
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return ((uint64_t)valhi << 32) | vallo;
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}
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static inline void
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nlm_store_dword(uint64_t addr, uint64_t val)
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{
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volatile uint64_t *p = (volatile uint64_t *)(long)addr;
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uint32_t valhi, vallo, sr;
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valhi = val >> 32;
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vallo = val & 0xffffffff;
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sr = nlm_save_flags_kx();
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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"dsll32 $8, %1, 0\n\t"
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"dsll32 $9, %2, 0\n\t" /* get rid of the */
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"dsrl32 $9, $9, 0\n\t" /* sign extend */
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"or $9, $9, $8\n\t"
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"sd $9, 0(%0)\n\t"
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".set pop\n"
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: : "r"(p), "r"(valhi), "r"(vallo)
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: "$8", "$9", "memory");
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nlm_restore_flags(sr);
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}
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#endif
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#if defined(__mips_n64)
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static inline uint64_t
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nlm_load_word_daddr(uint64_t addr)
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{
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volatile uint32_t *p = (volatile uint32_t *)(long)addr;
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return *p;
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}
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static inline void
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nlm_store_word_daddr(uint64_t addr, uint32_t val)
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{
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volatile uint32_t *p = (volatile uint32_t *)(long)addr;
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*p = val;
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}
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static inline uint64_t
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nlm_load_dword_daddr(uint64_t addr)
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{
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volatile uint64_t *p = (volatile uint64_t *)(long)addr;
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return *p;
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}
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static inline void
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nlm_store_dword_daddr(uint64_t addr, uint64_t val)
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{
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volatile uint64_t *p = (volatile uint64_t *)(long)addr;
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*p = val;
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}
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#elif defined(__mips_n32)
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static inline uint64_t
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nlm_load_word_daddr(uint64_t addr)
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{
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uint32_t val;
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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"lw %0, 0(%1)\n\t"
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".set pop\n"
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: "=r"(val)
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: "r"(addr));
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return val;
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}
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static inline void
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nlm_store_word_daddr(uint64_t addr, uint32_t val)
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{
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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"sw %0, 0(%1)\n\t"
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".set pop\n"
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: : "r"(val), "r"(addr)
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: "memory");
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}
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static inline uint64_t
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nlm_load_dword_daddr(uint64_t addr)
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{
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uint64_t val;
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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"ld %0, 0(%1)\n\t"
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".set pop\n"
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: "=r"(val)
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: "r"(addr));
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return val;
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}
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static inline void
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nlm_store_dword_daddr(uint64_t addr, uint64_t val)
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{
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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"sd %0, 0(%1)\n\t"
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".set pop\n"
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: : "r"(val), "r"(addr)
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: "memory");
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}
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#else /* o32 */
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static inline uint64_t
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nlm_load_word_daddr(uint64_t addr)
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{
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uint32_t val, addrhi, addrlo, sr;
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addrhi = addr >> 32;
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addrlo = addr & 0xffffffff;
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sr = nlm_save_flags_kx();
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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"dsll32 $8, %1, 0\n\t"
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"dsll32 $9, %2, 0\n\t"
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"dsrl32 $9, $9, 0\n\t"
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"or $9, $9, $8\n\t"
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"lw %0, 0($9)\n\t"
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".set pop\n"
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: "=r"(val)
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: "r"(addrhi), "r"(addrlo)
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: "$8", "$9");
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nlm_restore_flags(sr);
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return val;
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}
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static inline void
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nlm_store_word_daddr(uint64_t addr, uint32_t val)
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{
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uint32_t addrhi, addrlo, sr;
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addrhi = addr >> 32;
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addrlo = addr & 0xffffffff;
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sr = nlm_save_flags_kx();
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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"dsll32 $8, %1, 0\n\t"
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"dsll32 $9, %2, 0\n\t"
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"dsrl32 $9, $9, 0\n\t"
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"or $9, $9, $8\n\t"
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"sw %0, 0($9)\n\t"
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".set pop\n"
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: : "r"(val), "r"(addrhi), "r"(addrlo)
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: "$8", "$9", "memory");
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nlm_restore_flags(sr);
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}
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static inline uint64_t
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nlm_load_dword_daddr(uint64_t addr)
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{
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uint32_t addrh, addrl, sr;
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uint32_t valh, vall;
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addrh = addr >> 32;
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addrl = addr & 0xffffffff;
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sr = nlm_save_flags_kx();
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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"dsll32 $8, %2, 0\n\t"
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"dsll32 $9, %3, 0\n\t"
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"dsrl32 $9, $9, 0\n\t"
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"or $9, $9, $8\n\t"
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"ld $8, 0($9)\n\t"
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"dsra32 %0, $8, 0\n\t"
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"sll %1, $8, 0\n\t"
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".set pop\n"
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: "=r"(valh), "=r"(vall)
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: "r"(addrh), "r"(addrl)
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: "$8", "$9");
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nlm_restore_flags(sr);
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return ((uint64_t)valh << 32) | vall;
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}
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static inline void
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nlm_store_dword_daddr(uint64_t addr, uint64_t val)
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{
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uint32_t addrh, addrl, sr;
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uint32_t valh, vall;
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addrh = addr >> 32;
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addrl = addr & 0xffffffff;
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valh = val >> 32;
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vall = val & 0xffffffff;
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sr = nlm_save_flags_kx();
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__asm__ __volatile__(
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".set push\n\t"
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".set mips64\n\t"
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"dsll32 $8, %2, 0\n\t"
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"dsll32 $9, %3, 0\n\t"
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"dsrl32 $9, $9, 0\n\t"
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"or $9, $9, $8\n\t"
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"dsll32 $8, %0, 0\n\t"
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"dsll32 $10, %1, 0\n\t"
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"dsrl32 $10, $10, 0\n\t"
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"or $8, $8, $10\n\t"
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"sd $8, 0($9)\n\t"
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".set pop\n"
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: : "r"(valh), "r"(vall), "r"(addrh), "r"(addrl)
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: "$8", "$9", "memory");
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nlm_restore_flags(sr);
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}
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#endif /* __mips_n64 */
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static inline uint32_t
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nlm_read_reg(uint64_t base, uint32_t reg)
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{
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volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
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return *addr;
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}
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static inline void
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nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val)
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{
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volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg;
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*addr = val;
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}
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static inline uint64_t
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nlm_read_reg64(uint64_t base, uint32_t reg)
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{
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uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
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return nlm_load_dword(addr);
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}
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static inline void
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nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val)
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{
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uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
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return nlm_store_dword(addr, val);
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}
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/*
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* Routines to store 32/64 bit values to 64 bit addresses,
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* used when going thru XKPHYS to access registers
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*/
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static inline uint32_t
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nlm_read_reg_xkphys(uint64_t base, uint32_t reg)
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{
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uint64_t addr = base + reg * sizeof(uint32_t);
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return nlm_load_word_daddr(addr);
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}
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static inline void
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nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val)
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{
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uint64_t addr = base + reg * sizeof(uint32_t);
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return nlm_store_word_daddr(addr, val);
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}
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static inline uint64_t
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nlm_read_reg64_xkphys(uint64_t base, uint32_t reg)
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{
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uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
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return nlm_load_dword_daddr(addr);
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}
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static inline void
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nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
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{
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uint64_t addr = base + (reg >> 1) * sizeof(uint64_t);
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return nlm_store_dword_daddr(addr, val);
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}
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/* Location where IO base is mapped */
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extern uint64_t xlp_io_base;
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static inline uint64_t
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nlm_pcicfg_base(uint32_t devoffset)
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{
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return xlp_io_base + devoffset;
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}
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static inline uint64_t
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nlm_xkphys_map_pcibar0(uint64_t pcibase)
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{
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uint64_t paddr;
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paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
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return (uint64_t)0x9000000000000000 | paddr;
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}
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#endif
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