1248f2322b
is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
435 lines
10 KiB
C
435 lines
10 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91_twireg.h>
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#include <arm/at91/at91_twiio.h>
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struct at91_twi_softc
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{
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device_t dev; /* Myself */
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void *intrhand; /* Interrupt handle */
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struct resource *irq_res; /* IRQ resource */
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struct resource *mem_res; /* Memory resource */
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struct mtx sc_mtx; /* basically a perimeter lock */
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int flags;
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#define XFER_PENDING 1 /* true when transfer taking place */
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#define OPENED 2 /* Device opened */
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#define RXRDY 4
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#define TXCOMP 8
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#define TXRDY 0x10
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struct cdev *cdev;
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uint32_t cwgr;
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};
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static inline uint32_t
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RD4(struct at91_twi_softc *sc, bus_size_t off)
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{
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return bus_read_4(sc->mem_res, off);
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}
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static inline void
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WR4(struct at91_twi_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_write_4(sc->mem_res, off, val);
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}
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#define AT91_TWI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define AT91_TWI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define AT91_TWI_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
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"twi", MTX_DEF)
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#define AT91_TWI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define AT91_TWI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED);
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#define AT91_TWI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
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#define CDEV2SOFTC(dev) ((dev)->si_drv1)
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#define TWI_DEF_CLK 100000
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static devclass_t at91_twi_devclass;
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/* bus entry points */
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static int at91_twi_probe(device_t dev);
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static int at91_twi_attach(device_t dev);
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static int at91_twi_detach(device_t dev);
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static void at91_twi_intr(void *);
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/* helper routines */
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static int at91_twi_activate(device_t dev);
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static void at91_twi_deactivate(device_t dev);
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/* cdev routines */
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static d_open_t at91_twi_open;
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static d_close_t at91_twi_close;
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static d_ioctl_t at91_twi_ioctl;
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static struct cdevsw at91_twi_cdevsw =
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{
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.d_version = D_VERSION,
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.d_open = at91_twi_open,
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.d_close = at91_twi_close,
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.d_ioctl = at91_twi_ioctl
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};
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static int
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at91_twi_probe(device_t dev)
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{
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device_set_desc(dev, "TWI");
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return (0);
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}
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static int
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at91_twi_attach(device_t dev)
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{
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struct at91_twi_softc *sc = device_get_softc(dev);
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int err;
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sc->dev = dev;
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err = at91_twi_activate(dev);
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if (err)
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goto out;
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AT91_TWI_LOCK_INIT(sc);
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/*
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* Activate the interrupt
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*/
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err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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at91_twi_intr, sc, &sc->intrhand);
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if (err) {
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AT91_TWI_LOCK_DESTROY(sc);
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goto out;
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}
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sc->cdev = make_dev(&at91_twi_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600,
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"twi%d", device_get_unit(dev));
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if (sc->cdev == NULL) {
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err = ENOMEM;
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goto out;
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}
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sc->cdev->si_drv1 = sc;
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sc->cwgr = TWI_CWGR_CKDIV(1) |
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TWI_CWGR_CHDIV(TWI_CWGR_DIV(TWI_DEF_CLK)) |
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TWI_CWGR_CLDIV(TWI_CWGR_DIV(TWI_DEF_CLK));
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WR4(sc, TWI_CR, TWI_CR_SWRST);
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WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
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WR4(sc, TWI_CWGR, sc->cwgr);
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out:;
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if (err)
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at91_twi_deactivate(dev);
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return (err);
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}
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static int
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at91_twi_detach(device_t dev)
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{
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return (EBUSY); /* XXX */
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}
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static int
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at91_twi_activate(device_t dev)
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{
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struct at91_twi_softc *sc;
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int rid;
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sc = device_get_softc(dev);
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL)
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goto errout;
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL)
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goto errout;
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return (0);
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errout:
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at91_twi_deactivate(dev);
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return (ENOMEM);
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}
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static void
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at91_twi_deactivate(device_t dev)
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{
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struct at91_twi_softc *sc;
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sc = device_get_softc(dev);
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if (sc->intrhand)
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bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
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sc->intrhand = 0;
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bus_generic_detach(sc->dev);
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if (sc->mem_res)
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bus_release_resource(dev, SYS_RES_IOPORT,
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rman_get_rid(sc->mem_res), sc->mem_res);
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sc->mem_res = 0;
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if (sc->irq_res)
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bus_release_resource(dev, SYS_RES_IRQ,
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rman_get_rid(sc->irq_res), sc->irq_res);
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sc->irq_res = 0;
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return;
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}
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static void
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at91_twi_intr(void *xsc)
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{
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struct at91_twi_softc *sc = xsc;
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uint32_t status;
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/* Reading the status also clears the interrupt */
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status = RD4(sc, TWI_SR);
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if (status == 0)
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return;
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AT91_TWI_LOCK(sc);
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if (status & TWI_SR_RXRDY)
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sc->flags |= RXRDY;
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if (status & TWI_SR_TXCOMP)
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sc->flags |= TXCOMP;
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if (status & TWI_SR_TXRDY)
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sc->flags |= TXRDY;
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AT91_TWI_UNLOCK(sc);
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wakeup(sc);
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return;
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}
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static int
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at91_twi_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
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{
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struct at91_twi_softc *sc;
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sc = CDEV2SOFTC(dev);
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AT91_TWI_LOCK(sc);
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if (!(sc->flags & OPENED)) {
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sc->flags |= OPENED;
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WR4(sc, TWI_IER, TWI_SR_TXCOMP | TWI_SR_RXRDY | TWI_SR_TXRDY |
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TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK);
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}
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AT91_TWI_UNLOCK(sc);
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return (0);
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}
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static int
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at91_twi_close(struct cdev *dev, int fflag, int devtype, struct thread *td)
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{
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struct at91_twi_softc *sc;
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sc = CDEV2SOFTC(dev);
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AT91_TWI_LOCK(sc);
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sc->flags &= ~OPENED;
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WR4(sc, TWI_IDR, TWI_SR_TXCOMP | TWI_SR_RXRDY | TWI_SR_TXRDY |
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TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK);
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AT91_TWI_UNLOCK(sc);
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return (0);
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}
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static int
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at91_twi_read_master(struct at91_twi_softc *sc, struct at91_twi_io *xfr)
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{
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uint8_t *walker;
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uint8_t buffer[256];
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size_t len;
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int err = 0;
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if (xfr->xfer_len > sizeof(buffer))
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return (EINVAL);
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walker = buffer;
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len = xfr->xfer_len;
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RD4(sc, TWI_RHR);
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// Master mode, with the right address and interal addr size
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WR4(sc, TWI_MMR, TWI_MMR_IADRSZ(xfr->iadrsz) | TWI_MMR_MREAD |
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TWI_MMR_DADR(xfr->dadr));
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WR4(sc, TWI_IADR, xfr->iadr);
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WR4(sc, TWI_CR, TWI_CR_START);
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while (len-- > 1) {
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while (!(sc->flags & RXRDY)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird",
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0);
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if (err)
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return (err);
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}
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sc->flags &= ~RXRDY;
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*walker++ = RD4(sc, TWI_RHR) & 0xff;
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}
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WR4(sc, TWI_CR, TWI_CR_STOP);
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while (!(sc->flags & TXCOMP)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twird2", 0);
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if (err)
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return (err);
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}
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sc->flags &= ~TXCOMP;
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*walker = RD4(sc, TWI_RHR) & 0xff;
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if (xfr->xfer_buf) {
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AT91_TWI_UNLOCK(sc);
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err = copyout(buffer, xfr->xfer_buf, xfr->xfer_len);
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AT91_TWI_LOCK(sc);
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}
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return (err);
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}
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static int
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at91_twi_write_master(struct at91_twi_softc *sc, struct at91_twi_io *xfr)
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{
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uint8_t *walker;
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uint8_t buffer[256];
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size_t len;
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int err;
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if (xfr->xfer_len > sizeof(buffer))
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return (EINVAL);
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walker = buffer;
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len = xfr->xfer_len;
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AT91_TWI_UNLOCK(sc);
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err = copyin(xfr->xfer_buf, buffer, xfr->xfer_len);
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AT91_TWI_LOCK(sc);
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if (err)
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return (err);
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/* Setup the xfr for later readback */
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xfr->xfer_buf = 0;
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xfr->xfer_len = 1;
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while (len--) {
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WR4(sc, TWI_MMR, TWI_MMR_IADRSZ(xfr->iadrsz) | TWI_MMR_MWRITE |
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TWI_MMR_DADR(xfr->dadr));
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WR4(sc, TWI_IADR, xfr->iadr++);
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WR4(sc, TWI_THR, *walker++);
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WR4(sc, TWI_CR, TWI_CR_START);
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/*
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* If we get signal while waiting for TXRDY, make sure we
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* try to stop this device
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*/
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while (!(sc->flags & TXRDY)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twiwr",
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0);
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if (err)
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break;
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}
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WR4(sc, TWI_CR, TWI_CR_STOP);
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if (err)
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return (err);
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while (!(sc->flags & TXCOMP)) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH, "twiwr2",
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0);
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if (err)
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return (err);
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}
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/* Readback */
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at91_twi_read_master(sc, xfr);
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}
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return (err);
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}
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static int
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at91_twi_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
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struct thread *td)
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{
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int err = 0;
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struct at91_twi_softc *sc;
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sc = CDEV2SOFTC(dev);
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AT91_TWI_LOCK(sc);
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while (sc->flags & XFER_PENDING) {
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err = msleep(sc, &sc->sc_mtx, PZERO | PCATCH,
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"twiwait", 0);
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if (err) {
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AT91_TWI_UNLOCK(sc);
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return (err);
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}
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}
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sc->flags |= XFER_PENDING;
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switch (cmd)
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{
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case TWIIOCXFER:
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{
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struct at91_twi_io *xfr = (struct at91_twi_io *)data;
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switch (xfr->type)
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{
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case TWI_IO_READ_MASTER:
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err = at91_twi_read_master(sc, xfr);
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break;
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case TWI_IO_WRITE_MASTER:
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err = at91_twi_write_master(sc, xfr);
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break;
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default:
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err = EINVAL;
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break;
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}
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break;
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}
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case TWIIOCSETCLOCK:
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{
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struct at91_twi_clock *twick = (struct at91_twi_clock *)data;
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sc->cwgr = TWI_CWGR_CKDIV(twick->ckdiv) |
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TWI_CWGR_CHDIV(TWI_CWGR_DIV(twick->high_rate)) |
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TWI_CWGR_CLDIV(TWI_CWGR_DIV(twick->low_rate));
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WR4(sc, TWI_CR, TWI_CR_SWRST);
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WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS);
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WR4(sc, TWI_CWGR, sc->cwgr);
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break;
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}
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default:
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err = ENOTTY;
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break;
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}
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sc->flags &= ~XFER_PENDING;
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AT91_TWI_UNLOCK(sc);
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wakeup(sc);
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return err;
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}
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static device_method_t at91_twi_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, at91_twi_probe),
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DEVMETHOD(device_attach, at91_twi_attach),
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DEVMETHOD(device_detach, at91_twi_detach),
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{ 0, 0 }
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};
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static driver_t at91_twi_driver = {
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"at91_twi",
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at91_twi_methods,
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sizeof(struct at91_twi_softc),
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};
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DRIVER_MODULE(at91_twi, atmelarm, at91_twi_driver, at91_twi_devclass, 0, 0);
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