5ad9ac037d
This unifies handling of core, chip, and board-level device matching, and adds support for matching device drivers against the bus attach type (e.g. SoC vs WiFi adapter). Core-level quirks on Broadcom's chipsets generally are specific to some combination of chip model, core revision, chip package (e.g. 12x9 SMT package), SROM revision, etc. Unifying the match APIs for all three attribute types (core, chip, board/srom) allows defining a single device quirk table that matches across all of those attributes. Submitted by: Landon Fuller <landonf@landonf.org> Differential Revision: https://reviews.freebsd.org/D6515
196 lines
5.5 KiB
C
196 lines
5.5 KiB
C
/*-
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* Copyright (c) 2015 Landon Fuller <landon@landonf.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <dev/bhnd/bhnd_ids.h>
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#include <dev/bhnd/bhndreg.h>
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#include <dev/bhnd/bhnd.h>
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#include "bhndb_hwdata.h"
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/*
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* Resource priority specifications shared by all bhndb(4) bridge
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* implementations.
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*/
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/*
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* Define a bhndb_port_priority table.
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*/
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#define BHNDB_PORTS(...) \
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.ports = _BHNDB_PORT_ARRAY(__VA_ARGS__), \
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.num_ports = nitems(_BHNDB_PORT_ARRAY(__VA_ARGS__))
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#define _BHNDB_PORT_ARRAY(...) (const struct bhndb_port_priority[]) { \
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__VA_ARGS__ \
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}
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/*
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* Define a core priority record for all cores matching @p devclass
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*/
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#define BHNDB_CLASS_PRIO(_devclass, _priority, ...) { \
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.match = { \
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BHND_MATCH_CORE_CLASS(BHND_DEVCLASS_ ## _devclass), \
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}, \
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.priority = (BHNDB_PRIORITY_ ## _priority), \
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BHNDB_PORTS(__VA_ARGS__) \
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}
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/*
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* Define a default core priority record
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*/
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#define BHNDB_DEFAULT_PRIO(...) { \
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.match = { \
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BHND_MATCH_ANY , \
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}, \
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.priority = (BHNDB_PRIORITY_DEFAULT), \
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BHNDB_PORTS(__VA_ARGS__) \
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}
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/* Define a port priority record for the type/port/region
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* triplet. */
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#define BHNDB_PORT_PRIO(_type, _port, _region, _priority) { \
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.type = (BHND_PORT_ ## _type), \
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.port = _port, \
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.region = _region, \
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.priority = (BHNDB_PRIORITY_ ## _priority) \
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}
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/* Define a port priority record for the default (_type, 0, 0) type/port/region
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* triplet. */
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#define BHNDB_PORT0_PRIO(_type, _priority) \
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BHNDB_PORT_PRIO(_type, 0, 0, _priority)
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/**
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* Generic resource priority configuration usable with all currently supported
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* bcma(4)-based PCI devices.
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*/
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const struct bhndb_hw_priority bhndb_bcma_priority_table[] = {
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/*
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* Ignorable device classes.
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*
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* Runtime access to these cores is not required, and no register
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* windows should be reserved for these device types.
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*/
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BHNDB_CLASS_PRIO(SOC_ROUTER, NONE),
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BHNDB_CLASS_PRIO(SOC_BRIDGE, NONE),
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BHNDB_CLASS_PRIO(EROM, NONE),
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BHNDB_CLASS_PRIO(OTHER, NONE),
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/*
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* Low priority device classes.
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*
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* These devices do not sit in a performance-critical path and can be
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* treated as a low allocation priority.
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*/
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BHNDB_CLASS_PRIO(CC, LOW,
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/* Device Block */
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BHNDB_PORT0_PRIO(DEVICE, LOW),
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/* CC agent registers are not accessed via the bridge. */
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BHNDB_PORT0_PRIO(AGENT, NONE)
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),
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BHNDB_CLASS_PRIO(PMU, LOW,
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/* Device Block */
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BHNDB_PORT0_PRIO(DEVICE, LOW),
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/* PMU agent registers are not accessed via the bridge. */
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BHNDB_PORT0_PRIO(AGENT, NONE)
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),
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/*
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* Default Core Behavior
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*
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* All other cores are assumed to require efficient runtime access to
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* the default device port, and if supported by the bus, an agent port.
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*/
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BHNDB_DEFAULT_PRIO(
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/* Device Block */
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BHNDB_PORT0_PRIO(DEVICE, HIGH),
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/* Agent Block */
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BHNDB_PORT0_PRIO(AGENT, DEFAULT)
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),
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BHNDB_HW_PRIORITY_TABLE_END
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};
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/**
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* Generic resource priority configuration usable with all currently supported
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* siba(4)-based PCI devices.
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*/
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const struct bhndb_hw_priority bhndb_siba_priority_table[] = {
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/*
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* Ignorable device classes.
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*
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* Runtime access to these cores is not required, and no register
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* windows should be reserved for these device types.
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*/
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BHNDB_CLASS_PRIO(SOC_ROUTER, NONE),
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BHNDB_CLASS_PRIO(SOC_BRIDGE, NONE),
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BHNDB_CLASS_PRIO(EROM, NONE),
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BHNDB_CLASS_PRIO(OTHER, NONE),
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/*
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* Low priority device classes.
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*
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* These devices do not sit in a performance-critical path and can be
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* treated as a low allocation priority.
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*
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* Agent ports are marked as 'NONE' on siba(4) devices, as they
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* will be fully mappable via register windows shared with the
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* device0.0 port.
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*/
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BHNDB_CLASS_PRIO(CC, LOW,
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/* Device Block */
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BHNDB_PORT_PRIO(DEVICE, 0, 0, LOW)
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),
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BHNDB_CLASS_PRIO(PMU, LOW,
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/* Device Block */
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BHNDB_PORT_PRIO(DEVICE, 0, 0, LOW)
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),
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/*
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* Default Core Behavior
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*
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* All other cores are assumed to require efficient runtime access to
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* the device port.
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*/
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BHNDB_DEFAULT_PRIO(
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/* Device Block */
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BHNDB_PORT_PRIO(DEVICE, 0, 0, HIGH)
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),
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BHNDB_HW_PRIORITY_TABLE_END
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}; |