c88fa71928
all public firmwares for all chips since the last release (1.15.37.0) follows (it's a straight copy-paste from the Release Notes for the 12/30/2016 Unified Wire release on Chelsio's website). T6 Firmware ++++++++++++ Version : 1.16.26.0 Date : 12/28/2016 Fixes ----- BASE: - Max number of egress and control queues adjusted to accomodate co-processor mode queues. - Fixed intermittent DDR3/4 ECC errors. - Fixed a traffic stall when ETS BW is configured as 0%. - Max number of ethctrl queue in VF set to 1. ETH: - Added a new config file option 'speed' under port section to set the port speed. Use only when auto negotiation is off. - FEC option removed from firmware config file. cxgbtool can be used to change the fec setting. - CPL_TX_TNL_LSO cpl handling added in ETH_TX_PKT_VM handler. This fixes large tunnel tcp packet support for VxLAN. Version : 1.16.22.0 Date : 12/05/2016 Fixes ----- BASE: - fw_port_type updated in fw API to match kernel.org definitions. - Saved power by disaling unused MAC lanes. - Configures correct power bin. - Enhanced DDR4 performance. - Enabled interrupts. - Fixed an issue where filter rule for 'unicast hash' is not working. ETH: - Disabled auto negotiation by default because most of 100G switches do not support AN as of today. - Fixed flow control not getting disabled problem. - Fixed an issue where port0 doesn't come up sometimes. - Fixed 10G link not coming up issue. - Fixed an issue with promiscuous mode when dcbx disabled. OFLD: - Fixed a connection stuck issue when abort is received during out of tx pages backpressure. ENHANCEMENTS ------------ BASE: - Added inline TLS mode support. Version : 1.16.12.0 Date : 11/11/2016 ENHANCEMENTS ------------ BASE: - Added T6 support. - Added T6 1G/10G/25G/40G/100G link speeds. - Added T6 co-processor mode crypto support. - Added facility to increase link AN+AEC timeout. OFLD: - Added support for all T5 offload protocols except FCoE. iSCSI: - iscsi completion moderation enabled. ======================================================================= T5 Firmware ++++++++++++ Version : 1.16.26.0 Date : 12/28/2016 FIXES ----- BASE: - Max number of ethctrl queue in VF set to 1. Version : 1.16.22.0 Date : 12/05/2016 FIXES ----- BASE: - Fixed an issue where filter rule for 'unicast hash' is not working. ETH: - Fixed an issue with promiscuous mode when dcbx disabled. ENHANCEMENTS ------------ ETH: - Added 40G-KR support. Version : 1.16.12.0 Date : 11/11/2016 FIXES ----- BASE: - Fixed multiple issues related with VFs FLR processing. - Fixed channel assignment based on number of ports in adapter. - Fixed a crash when VM having PF assigned as passthrough mode is rebooted. - Handled 2nd HELLO command from the same PF without seeing BYE from the same PF and if that is the only PF. - A warning is printed in firmware log if PCI-E cookie generation is enabled in serial initialization file. - Fixed multiple issues related with Filtering. - Enabled DSGL memory write for iscsi and rdma. - Added new FW_PARAMS_CMD[DEV] options to retrieve Serial Configuration and VPD version numbers. - Fixed an issue where LVDS output was not getting enabled using vpd. DCBX: - Fixed DCBX CEE Incorrect class to pririty mapping. - Fixed incorrect interpretation of DCBX IEEE PFC. ETH: - Adjusted the link related delay timings according to the QSFP spec. - Improved 40G link bringup time with few switches. OFLD: - Do not reserve qp/cq if rdma capability is not enabled. - Fixed an issue where approx 1600+ TOE connections were causing a firmware fatal error. FOiSCSI: - Fixed an issue where unloading foiscsi driver causes mailbox timeout. ENHANCEMENTS ------------ BASE: - Added 10G KR/KX support. - Added T540-BT adapter support. - Added 4 new rss key modes for PFs and VFs. OFLD: - Added new WR FW_RI_FR_NSMR_TPTE_WR to improve fast MR write performance in RDMA. Version : 1.16.5.0 Date : 10/26/2016 FIXES ----- BASE: - Fixed multiple issues where FLR from multiple VFs can cause firmware crash. - Fixed channel assignment based on number of ports in adapter. - Fixed the HELLO command master force api to handle the 2nd HELLO correctly without getting BYE from the PF driver. - Added facility to retrieve Serial configuration and VPD version. Two new FW_PARAMS_CMD[DEV] options added to retrieve these values. - Fixed multiple issues where FLR from multiple VFs are not completing. - Added new RSS hash secret key modes. - Fixed an issue where LVDS output was not getting enabled using vpd. DCBX: - Fixed an issue where iscsi tlv is sent incorrectly to host (DCBX CEE). - Fixed an issue where app priority values are not handled correctly in fw (DCBX IEEE). ETH: - Adjusts the link related delay timings according to the QSFP spec. - Changed 2.5G mac speed bit to 25G mac speed bit in fw API. - Improvement in 40G link bringup time with few switches. OFLD: - Do not reserve qp/cq if rdma capability is not enabled. - Fixed an issue where approx 1600+ TOE connections were causing a firmware fatal error. - Fixed DSGL memory write in T5. Now iwarp and iscsi can use DSGL to do memory write. - Fixed multiple issues in hash filter mode where incorrect protocol mask was getting used and affecting hash filter functionality. - New fastpath WR FW_RI_FR_NSMR_TPTE_WR (with fully populated TPTE) is added for small REG_MR operations. FOiSCSI: - Fixed an issue in foiscsi recovery path. - Fixed an issue where foiscsi (in VM in PCIE passthrough mode) didn't come up after VM FLR. ENHANCEMENTS ------------ ETH: - Implemented 1G/10G KR/KX ability. - Implemented T540-BT adapter support. ======================================================================= T4 Firmware +++++++++++ Version : 1.16.12.0 Date : 11/11/2016 FIXES ----- BASE: - Fixed an issue where reading temperature sesors using ldst command causes mailbox timeout. - Added new FW_PARAMS_CMD[DEV] options to retrieve Serial Configuration and VPD version numbers. ETH: - Fixed DCBX CEE Incorrect class to pririty mapping. FOiSCSI: - Fixed an issue where unloading foiscsi driver causes mailbox timeout. MFC after: 3 days Sponsored by: Chelsio Communications
285 lines
5.7 KiB
Plaintext
285 lines
5.7 KiB
Plaintext
# Firmware configuration file.
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#
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# Global limits (some are hardware limits, others are due to the firmware).
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# nvi = 128 virtual interfaces
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# niqflint = 1023 ingress queues with freelists and/or interrupts
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# nethctrl = 64K Ethernet or ctrl egress queues
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# neq = 64K egress queues of all kinds, including freelists
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# nexactf = 512 MPS TCAM entries, can oversubscribe.
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[global]
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rss_glb_config_mode = basicvirtual
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rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
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# PL_TIMEOUT register
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pl_timeout_value = 200 # the timeout value in units of us
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sge_timer_value = 1, 5, 10, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
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reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
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reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
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#Tick granularities in kbps
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tsch_ticks = 100000, 10000, 1000, 10
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filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe
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filterMask = protocol
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tp_pmrx = 36, 512
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tp_pmrx_pagesize = 64K
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# TP number of RX channels (0 = auto)
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tp_nrxch = 0
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tp_pmtx = 46, 512
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tp_pmtx_pagesize = 64K
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# TP number of TX channels (0 = auto)
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tp_ntxch = 0
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# TP OFLD MTUs
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tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
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# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
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reg[0x7d04] = 0x00010008/0x00010008
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# TP_GLOBAL_CONFIG
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reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
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# TP_PC_CONFIG
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reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
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# TP_PARA_REG0
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reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
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# cluster, lan, or wan.
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tp_tcptuning = lan
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# LE_DB_CONFIG
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reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled
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# LE IPv4 compression disabled
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# LE_DB_HASH_CONFIG
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reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
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# ULP_TX_CONFIG
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reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err
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# Enable more error msg for ...
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# TPT error.
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# ULP_RX_MISC_FEATURE_ENABLE
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#reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit
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# Enable offset decrement after ...
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# PI extraction and before DDP
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# ulp insert pi source info in DIF
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# iscsi_eff_offset_en
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#Enable iscsi completion moderation feature
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reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after
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# PI extraction and before DDP.
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# ulp insert pi source info in
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# DIF.
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# Enable iscsi hdr cmd mode.
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# iscsi force cmd mode.
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# Enable iscsi cmp mode.
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# MC configuration
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#mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
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# PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by
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# these 4 PFs only.
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[function "0"]
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nvf = 4
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wx_caps = all
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r_caps = all
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nvi = 2
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rssnvi = 2
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niqflint = 4
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nethctrl = 4
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neq = 8
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nexactf = 4
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cmask = all
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pmask = 0x1
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[function "1"]
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nvf = 4
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wx_caps = all
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r_caps = all
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nvi = 2
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rssnvi = 2
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niqflint = 4
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nethctrl = 4
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neq = 8
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nexactf = 4
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cmask = all
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pmask = 0x2
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[function "2"]
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nvf = 4
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wx_caps = all
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r_caps = all
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nvi = 2
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rssnvi = 2
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niqflint = 4
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nethctrl = 4
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neq = 8
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nexactf = 4
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cmask = all
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pmask = 0x4
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[function "3"]
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nvf = 4
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wx_caps = all
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r_caps = all
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nvi = 2
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rssnvi = 2
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niqflint = 4
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nethctrl = 4
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neq = 8
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nexactf = 4
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cmask = all
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pmask = 0x8
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# PF4 is the resource-rich PF that the bus/nexus driver attaches to.
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# It gets 32 MSI/128 MSI-X vectors.
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[function "4"]
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wx_caps = all
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r_caps = all
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nvi = 32
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rssnvi = 8
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niqflint = 512
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nethctrl = 1024
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neq = 2048
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nqpcq = 8192
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nexactf = 456
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cmask = all
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pmask = all
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nclip = 320
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# TCAM has 6K cells; each region must start at a multiple of 128 cell.
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# Each entry in these categories takes 2 cells each. nhash will use the
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# TCAM iff there is room left (that is, the rest don't add up to 3072).
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nfilter = 2032
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nserver = 512
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nhpfilter = 0
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nhash = 16384
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protocol = ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif
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tp_l2t = 4096
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tp_ddp = 2
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tp_ddp_iscsi = 2
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tp_stag = 2
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tp_pbl = 5
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tp_rq = 7
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tp_srq = 128
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# PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors.
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# Not used right now.
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[function "5"]
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nvi = 1
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rssnvi = 0
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# PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors.
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# Not used right now.
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[function "6"]
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nvi = 1
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rssnvi = 0
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# The following function, 1023, is not an actual PCIE function but is used to
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# configure and reserve firmware internal resources that come from the global
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# resource pool.
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#
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[function "1023"]
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wx_caps = all
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r_caps = all
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nvi = 4
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rssnvi = 0
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cmask = all
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pmask = all
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nexactf = 8
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nfilter = 16
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# For Virtual functions, we only allow NIC functionality and we only allow
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# access to one port (1 << PF). Note that because of limitations in the
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# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
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# and GTS registers, the number of Ingress and Egress Queues must be a power
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# of 2.
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#
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[function "0/*"]
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wx_caps = 0x82
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r_caps = 0x86
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nvi = 1
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rssnvi = 1
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x1
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[function "1/*"]
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wx_caps = 0x82
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r_caps = 0x86
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nvi = 1
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rssnvi = 1
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x2
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[function "2/*"]
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wx_caps = 0x82
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r_caps = 0x86
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nvi = 1
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rssnvi = 1
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x1
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[function "3/*"]
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wx_caps = 0x82
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r_caps = 0x86
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nvi = 1
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rssnvi = 1
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niqflint = 2
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nethctrl = 2
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neq = 4
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nexactf = 2
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cmask = all
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pmask = 0x2
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# MPS has 192K buffer space for ingress packets from the wire as well as
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# loopback path of the L2 switch.
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[port "0"]
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dcb = none
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#bg_mem = 25
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#lpbk_mem = 25
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hwm = 60
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lwm = 15
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dwm = 30
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#aec_retry_cnt = 4
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flags = an_dis
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[port "1"]
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dcb = none
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#bg_mem = 25
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#lpbk_mem = 25
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hwm = 60
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lwm = 15
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dwm = 30
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#aec_retry_cnt = 4
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flags = an_dis
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[fini]
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version = 0x1
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checksum = 0xd4ef7f0
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#
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# $FreeBSD$
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#
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