8256655132
noticed some major enhancements available for UP situations. The number of UP TLB flushes is decreased much more than significantly with these changes. Since a TLB flush appears to cost minimally approx 80 cycles, this is a "nice" enhancement, equiv to eliminating between 40 and 160 instructions per TLB flush. Changes include making sure that kernel threads all use the same PTD, and eliminate unneeded PTD switches at context switch time.
437 lines
10 KiB
C
437 lines
10 KiB
C
/*-
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* Copyright (c) 1993 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: cpufunc.h,v 1.72 1997/09/07 22:01:27 fsmp Exp $
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*/
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/*
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* Functions to provide access to special i386 instructions.
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <machine/lock.h>
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#if defined(SWTCH_OPTIM_STATS)
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extern int tlb_flush_count;
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#endif
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#ifdef __GNUC__
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static __inline void
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breakpoint(void)
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{
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__asm __volatile("int $3");
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}
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static __inline void
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disable_intr(void)
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{
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__asm __volatile("cli" : : : "memory");
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MPINTR_LOCK();
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}
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static __inline void
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enable_intr(void)
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{
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MPINTR_UNLOCK();
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__asm __volatile("sti");
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}
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#define HAVE_INLINE_FFS
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static __inline int
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ffs(int mask)
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{
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int result;
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/*
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* bsfl turns out to be not all that slow on 486's. It can beaten
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* using a binary search to reduce to 4 bits and then a table lookup,
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* but only if the code is inlined and in the cache, and the code
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* is quite large so inlining it probably busts the cache.
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*
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* Note that gcc-2's builtin ffs would be used if we didn't declare
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* this inline or turn off the builtin. The builtin is faster but
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* broken in gcc-2.4.5 and slower but working in gcc-2.5 and 2.6.
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*/
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__asm __volatile("testl %0,%0; je 1f; bsfl %0,%0; incl %0; 1:"
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: "=r" (result) : "0" (mask));
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return (result);
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}
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#define HAVE_INLINE_FLS
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static __inline int
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fls(int mask)
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{
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int result;
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__asm __volatile("testl %0,%0; je 1f; bsrl %0,%0; incl %0; 1:"
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: "=r" (result) : "0" (mask));
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return (result);
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}
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#if __GNUC__ < 2
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#define inb(port) inbv(port)
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#define outb(port, data) outbv(port, data)
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#else /* __GNUC >= 2 */
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/*
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* The following complications are to get around gcc not having a
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* constraint letter for the range 0..255. We still put "d" in the
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* constraint because "i" isn't a valid constraint when the port
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* isn't constant. This only matters for -O0 because otherwise
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* the non-working version gets optimized away.
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*
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* Use an expression-statement instead of a conditional expression
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* because gcc-2.6.0 would promote the operands of the conditional
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* and produce poor code for "if ((inb(var) & const1) == const2)".
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*
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* The unnecessary test `(port) < 0x10000' is to generate a warning if
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* the `port' has type u_short or smaller. Such types are pessimal.
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* This actually only works for signed types. The range check is
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* careful to avoid generating warnings.
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*/
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#define inb(port) __extension__ ({ \
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u_char _data; \
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if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
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&& (port) < 0x10000) \
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_data = inbc(port); \
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else \
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_data = inbv(port); \
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_data; })
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#define outb(port, data) ( \
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__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
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&& (port) < 0x10000 \
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? outbc(port, data) : outbv(port, data))
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static __inline u_char
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inbc(u_int port)
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{
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u_char data;
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__asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
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return (data);
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}
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static __inline void
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outbc(u_int port, u_char data)
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{
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__asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
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}
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#endif /* __GNUC <= 2 */
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static __inline u_char
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inbv(u_int port)
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{
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u_char data;
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/*
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* We use %%dx and not %1 here because i/o is done at %dx and not at
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* %edx, while gcc generates inferior code (movw instead of movl)
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* if we tell it to load (u_short) port.
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*/
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__asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
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return (data);
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}
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static __inline u_long
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inl(u_int port)
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{
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u_long data;
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__asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
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return (data);
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}
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static __inline void
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insb(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; insb"
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: : "d" (port), "D" (addr), "c" (cnt)
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: "di", "cx", "memory");
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}
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static __inline void
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insw(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; insw"
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: : "d" (port), "D" (addr), "c" (cnt)
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: "di", "cx", "memory");
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}
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static __inline void
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insl(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; insl"
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: : "d" (port), "D" (addr), "c" (cnt)
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: "di", "cx", "memory");
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}
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static __inline void
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invd(void)
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{
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__asm __volatile("invd");
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}
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#ifdef KERNEL
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#ifdef SMP
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/*
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* When using APIC IPI's, the inlining cost is prohibitive since the call
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* executes into the IPI transmission system.
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*/
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void invlpg __P((u_int addr));
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void invltlb __P((void));
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#else /* !SMP */
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static __inline void
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invlpg(u_int addr)
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{
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__asm __volatile("invlpg (%0)" : : "r" (addr) : "memory");
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}
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static __inline void
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invltlb(void)
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{
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u_long temp;
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/*
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* This should be implemented as load_cr3(rcr3()) when load_cr3()
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* is inlined.
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*/
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__asm __volatile("movl %%cr3, %0; movl %0, %%cr3" : "=r" (temp)
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: : "memory");
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#if defined(SWTCH_OPTIM_STATS)
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++tlb_flush_count;
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#endif
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}
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#endif /* SMP */
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#endif /* KERNEL */
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static __inline u_short
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inw(u_int port)
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{
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u_short data;
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__asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
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return (data);
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}
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static __inline u_int
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loadandclear(u_int *addr)
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{
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u_int result;
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__asm __volatile("xorl %0,%0; xchgl %1,%0"
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: "=&r" (result) : "m" (*addr));
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return (result);
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}
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static __inline void
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outbv(u_int port, u_char data)
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{
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u_char al;
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/*
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* Use an unnecessary assignment to help gcc's register allocator.
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* This make a large difference for gcc-1.40 and a tiny difference
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* for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
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* best results. gcc-2.6.0 can't handle this.
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*/
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al = data;
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__asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
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}
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static __inline void
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outl(u_int port, u_long data)
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{
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/*
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* outl() and outw() aren't used much so we haven't looked at
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* possible micro-optimizations such as the unnecessary
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* assignment for them.
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*/
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__asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
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}
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static __inline void
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outsb(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; outsb"
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: : "d" (port), "S" (addr), "c" (cnt)
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: "si", "cx");
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}
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static __inline void
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outsw(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; outsw"
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: : "d" (port), "S" (addr), "c" (cnt)
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: "si", "cx");
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}
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static __inline void
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outsl(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; outsl"
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: : "d" (port), "S" (addr), "c" (cnt)
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: "si", "cx");
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}
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static __inline void
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outw(u_int port, u_short data)
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{
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__asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
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}
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static __inline u_long
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rcr2(void)
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{
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u_long data;
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__asm __volatile("movl %%cr2,%0" : "=r" (data));
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return (data);
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}
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static __inline u_long
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read_eflags(void)
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{
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u_long ef;
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__asm __volatile("pushfl; popl %0" : "=r" (ef));
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return (ef);
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}
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static __inline quad_t
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rdmsr(u_int msr)
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{
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quad_t rv;
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__asm __volatile(".byte 0x0f, 0x32" : "=A" (rv) : "c" (msr));
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return (rv);
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}
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static __inline quad_t
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rdpmc(u_int pmc)
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{
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quad_t rv;
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__asm __volatile(".byte 0x0f, 0x33" : "=A" (rv) : "c" (pmc));
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return (rv);
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}
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static __inline quad_t
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rdtsc(void)
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{
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quad_t rv;
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__asm __volatile(".byte 0x0f, 0x31" : "=A" (rv));
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return (rv);
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}
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static __inline void
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setbits(volatile unsigned *addr, u_int bits)
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{
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__asm __volatile(
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#ifdef SMP
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"lock; "
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#endif
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"orl %1,%0" : "=m" (*addr) : "ir" (bits));
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}
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static __inline void
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wbinvd(void)
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{
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__asm __volatile("wbinvd");
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}
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static __inline void
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write_eflags(u_long ef)
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{
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__asm __volatile("pushl %0; popfl" : : "r" (ef));
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}
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static __inline void
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wrmsr(u_int msr, quad_t newval)
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{
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__asm __volatile(".byte 0x0f, 0x30" : : "A" (newval), "c" (msr));
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}
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#else /* !__GNUC__ */
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int breakpoint __P((void));
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void disable_intr __P((void));
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void enable_intr __P((void));
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u_char inb __P((u_int port));
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u_long inl __P((u_int port));
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void insb __P((u_int port, void *addr, size_t cnt));
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void insl __P((u_int port, void *addr, size_t cnt));
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void insw __P((u_int port, void *addr, size_t cnt));
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void invd __P((void));
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void invlpg __P((u_int addr));
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void invltlb __P((void));
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u_short inw __P((u_int port));
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u_int loadandclear __P((u_int *addr));
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void outb __P((u_int port, u_char data));
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void outl __P((u_int port, u_long data));
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void outsb __P((u_int port, void *addr, size_t cnt));
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void outsl __P((u_int port, void *addr, size_t cnt));
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void outsw __P((u_int port, void *addr, size_t cnt));
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void outw __P((u_int port, u_short data));
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u_long rcr2 __P((void));
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quad_t rdmsr __P((u_int msr));
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quad_t rdpmc __P((u_int pmc));
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quad_t rdtsc __P((void));
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u_long read_eflags __P((void));
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void setbits __P((volatile unsigned *addr, u_int bits));
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void wbinvd __P((void));
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void write_eflags __P((u_long ef));
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void wrmsr __P((u_int msr, quad_t newval));
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#endif /* __GNUC__ */
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void load_cr0 __P((u_long cr0));
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void load_cr3 __P((u_long cr3));
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void load_cr4 __P((u_long cr4));
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void ltr __P((u_short sel));
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u_int rcr0 __P((void));
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u_long rcr3 __P((void));
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u_long rcr4 __P((void));
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#endif /* !_MACHINE_CPUFUNC_H_ */
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