d212022417
o recognize ixp435 cpu o change memory layout for for ixp4xx to not assume memory is aliases to 0x10000000 (Cambria/ixp435 memory starts at zero) o handle 64 irqs for ixp435 o dual EHCI USB 2.0 controller integral to ixp435 o overhaul NPE code for ixp435 and better MAC+MII naming o updated NPE firmware (including NPE-A image for ixp435/ixp465) o Gateworks Cambria board support: - IDE compact flash - MCU - front panel LED on i2c bus - Octal LED latch Sanity-tested with NFS-root on Avila and Cambria boards. Requires pending boot2 mods for CF-boot on Cambria.
119 lines
3.3 KiB
C
119 lines
3.3 KiB
C
/*-
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* Copyright (c) 2006 Sam Leffler. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* IXP4XX Watchdog Timer Support.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/time.h>
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#include <sys/bus.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/frame.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <arm/xscale/ixp425/ixp425reg.h>
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#include <arm/xscale/ixp425/ixp425var.h>
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struct ixpwdog_softc {
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device_t sc_dev;
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};
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static __inline uint32_t
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RD4(struct ixpwdog_softc *sc, bus_size_t off)
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{
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return bus_space_read_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, off);
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}
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static __inline void
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WR4(struct ixpwdog_softc *sc, bus_size_t off, uint32_t val)
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{
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bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, off, val);
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}
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static void
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ixp425_watchdog(void *arg, u_int cmd, int *error)
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{
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struct ixpwdog_softc *sc = arg;
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u_int u = cmd & WD_INTERVAL;
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WR4(sc, IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK);
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if (4 <= u && u <= 35) {
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WR4(sc, IXP425_OST_WDOG_ENAB, 0);
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/* approximate 66.66MHz cycles */
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WR4(sc, IXP425_OST_WDOG, 2<<(u - 4));
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/* NB: reset on timer expiration */
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WR4(sc, IXP425_OST_WDOG_ENAB,
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OST_WDOG_ENAB_CNT_ENA | OST_WDOG_ENAB_RST_ENA);
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*error = 0;
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} else {
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/* disable watchdog */
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WR4(sc, IXP425_OST_WDOG_ENAB, 0);
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}
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WR4(sc, IXP425_OST_WDOG_KEY, 0);
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}
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static int
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ixpwdog_probe(device_t dev)
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{
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device_set_desc(dev, "IXP4XX Watchdog Timer");
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return (0);
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}
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static int
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ixpwdog_attach(device_t dev)
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{
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struct ixpwdog_softc *sc = device_get_softc(dev);
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sc->sc_dev = dev;
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EVENTHANDLER_REGISTER(watchdog_list, ixp425_watchdog, sc, 0);
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return (0);
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}
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static device_method_t ixpwdog_methods[] = {
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DEVMETHOD(device_probe, ixpwdog_probe),
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DEVMETHOD(device_attach, ixpwdog_attach),
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{0, 0},
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};
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static driver_t ixpwdog_driver = {
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"ixpwdog",
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ixpwdog_methods,
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sizeof(struct ixpwdog_softc),
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};
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static devclass_t ixpwdog_devclass;
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DRIVER_MODULE(ixpwdog, ixp, ixpwdog_driver, ixpwdog_devclass, 0, 0);
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