d4aba0f611
The CMS output queue credit configuration register is 64 bit, so use a 64 bit variable while updating it. Obtained from: Venkatesh J V <venkatesh.vivekanandan@broadcom.com>
355 lines
11 KiB
C
355 lines
11 KiB
C
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <machine/cpufunc.h>
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#include <mips/nlm/hal/mips-extns.h>
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#include <mips/nlm/hal/haldefs.h>
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#include <mips/nlm/hal/iomap.h>
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#include <mips/nlm/hal/fmn.h>
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/* XLP can take upto 16K of FMN messages per hardware queue, as spill.
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* But, configuring all 16K causes the total spill memory to required
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* to blow upto 192MB for single chip configuration, and 768MB in four
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* chip configuration. Hence for now, we will setup the per queue spill
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* as 1K FMN messages. With this, the total spill memory needed for 1024
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* hardware queues (with 12bytes per single entry FMN message) becomes
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* (1*1024)*12*1024queues = 12MB. For the four chip config, the memory
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* needed = 12 * 4 = 48MB.
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*/
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uint64_t nlm_cms_spill_total_messages = 1 * 1024;
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/* On a XLP832, we have the following FMN stations:
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* CPU stations: 8
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* PCIE0 stations: 1
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* PCIE1 stations: 1
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* PCIE2 stations: 1
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* PCIE3 stations: 1
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* GDX stations: 1
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* CRYPTO stations: 1
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* RSA stations: 1
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* CMP stations: 1
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* POE stations: 1
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* NAE stations: 1
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* ==================
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* Total : 18 stations per chip
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*
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* For all 4 nodes, there are 18*4 = 72 FMN stations
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*/
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uint32_t nlm_cms_total_stations = 18 * 4 /*xlp_num_nodes*/;
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/**
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* Takes inputs as node, queue_size and maximum number of queues.
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* Calculates the base, start & end and returns the same for a
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* defined qid.
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*
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* The output queues are maintained in the internal output buffer
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* which is a on-chip SRAM structure. For the actial hardware
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* internal implementation, It is a structure which consists
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* of eight banks of 4096-entry x message-width SRAMs. The SRAM
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* implementation is designed to run at 1GHz with a 1-cycle read/write
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* access. A read/write transaction can be initiated for each bank
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* every cycle for a total of eight accesses per cycle. Successive
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* entries of the same output queue are placed in successive banks.
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* This is done to spread different read & write accesses to same/different
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* output queue over as many different banks as possible so that they
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* can be scheduled concurrently. Spreading the accesses to as many banks
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* as possible to maximize the concurrency internally is important for
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* achieving the desired peak throughput. This is done by h/w implementation
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* itself.
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*
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* Output queues are allocated from this internal output buffer by
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* software. The total capacity of the output buffer is 32K-entry.
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* Each output queue can be sized from 32-entry to 1024-entry in
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* increments of 32-entry. This is done by specifying a Start & a
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* End pointer: pointers to the first & last 32-entry chunks allocated
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* to the output queue.
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*
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* To optimize the storage required for 1024 OQ pointers, the upper 5-bits
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* are shared by the Start & the End pointer. The side-effect of this
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* optimization is that an OQ can't cross a 1024-entry boundary. Also, the
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* lower 5-bits don't need to be specified in the Start & the End pointer
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* as the allocation is in increments of 32-entries.
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*
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* Queue occupancy is tracked by a Head & a Tail pointer. Tail pointer
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* indicates the location to which next entry will be written & Head
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* pointer indicates the location from which next entry will be read. When
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* these pointers reach the top of the allocated space (indicated by the
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* End pointer), they are reset to the bottom of the allocated space
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* (indicated by the Start pointer).
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*
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* Output queue pointer information:
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* 14 10 9 5 4 0
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* ------------------
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* | base ptr |
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* ------------------
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* ----------------
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* | start ptr |
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* ----------------
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* ----------------
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* | end ptr |
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* ----------------
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* ------------------------------------
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* | head ptr |
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* ------------------------------------
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* ------------------------------------
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* | tail ptr |
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* ------------------------------------
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* Note:
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* A total of 1024 segments can sit on one software-visible "bank"
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* of internal SRAM. Each segment contains 32 entries. Also note
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* that sw-visible "banks" are not the same as the actual internal
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* 8-bank implementation of hardware. It is an optimization of
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* internal access.
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*
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*/
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void nlm_cms_setup_credits(uint64_t base, int destid, int srcid, int credit)
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{
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uint64_t val;
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val = (((uint64_t)credit << 24) | (destid << 12) | (srcid << 0));
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nlm_write_cms_reg(base, CMS_OUTPUTQ_CREDIT_CFG, val);
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}
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/*
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* base - CMS module base address for this node.
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* qid - is the output queue id otherwise called as vc id
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* spill_base - is the 40-bit physical address of spill memory. Must be
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4KB aligned.
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* nsegs - No of segments where a "1" indicates 4KB. Spill size must be
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* a multiple of 4KB.
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*/
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int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base,
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int nsegs)
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{
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uint64_t queue_config;
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uint32_t spill_start;
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if (nsegs > CMS_MAX_SPILL_SEGMENTS_PER_QUEUE) {
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return 1;
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}
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queue_config = nlm_read_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)));
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spill_start = ((spill_base >> 12) & 0x3F);
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/* Spill configuration */
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queue_config = (((uint64_t)CMS_SPILL_ENA << 62) |
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(((spill_base >> 18) & 0x3FFFFF) << 27) |
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(spill_start + nsegs - 1) << 21 |
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(spill_start << 15));
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nlm_write_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)),queue_config);
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return 0;
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}
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uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid)
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{
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return nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
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}
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void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val)
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{
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uint64_t rdval;
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rdval = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
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rdval |= val;
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nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), rdval);
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}
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void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type,
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int intr_val)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
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val &= ~((0x7ULL << 56) | (0x3ULL << 54));
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val |= (((uint64_t)sub_type<<54) |
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((uint64_t)intr_val<<56));
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nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
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}
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void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type,
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int intr_val)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
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val &= ~((0x7ULL << 51) | (0x3ULL << 49));
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val |= (((uint64_t)sub_type<<49) |
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((uint64_t)intr_val<<51));
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nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
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}
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/* returns 1 if interrupt has been generated for this output queue */
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int nlm_cms_outputq_intr_check(uint64_t base, int qid)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
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return ((val >> 59) & 0x1);
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}
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void nlm_cms_outputq_clr_intr(uint64_t base, int qid)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
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val |= (1ULL<<59);
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nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
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}
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void nlm_cms_illegal_dst_error_intr(uint64_t base, int en)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
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val |= (en<<8);
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nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
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}
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void nlm_cms_timeout_error_intr(uint64_t base, int en)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
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val |= (en<<7);
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nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
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}
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void nlm_cms_biu_error_resp_intr(uint64_t base, int en)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
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val |= (en<<6);
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nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
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}
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void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
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val |= (en<<5) | (en<<3);
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nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
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}
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void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
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val |= (en<<4) | (en<<2);
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nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
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}
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void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
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val |= (en<<1);
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nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
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}
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void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en)
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{
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uint64_t val;
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val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
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val |= (en<<0);
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nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
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}
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uint64_t nlm_cms_network_error_status(uint64_t base)
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{
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return nlm_read_cms_reg(base, CMS_MSG_ERR);
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}
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int nlm_cms_get_net_error_code(uint64_t err)
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{
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return ((err >> 12) & 0xf);
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}
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int nlm_cms_get_net_error_syndrome(uint64_t err)
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{
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return ((err >> 32) & 0x1ff);
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}
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int nlm_cms_get_net_error_ramindex(uint64_t err)
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{
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return ((err >> 44) & 0x7fff);
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}
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int nlm_cms_get_net_error_outputq(uint64_t err)
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{
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return ((err >> 16) & 0xfff);
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}
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/*========================= FMN Tracing related APIs ================*/
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void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base,
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uint64_t trace_limit, int match_dstid_en,
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int dst_id, int match_srcid_en, int src_id,
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int wrap)
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{
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uint64_t val;
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nlm_write_cms_reg(base, CMS_TRACE_BASE_ADDR, trace_base);
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nlm_write_cms_reg(base, CMS_TRACE_LIMIT_ADDR, trace_limit);
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val = nlm_read_cms_reg(base, CMS_TRACE_CONFIG);
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val |= (((uint64_t)match_dstid_en << 39) |
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((dst_id & 0xfff) << 24) |
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(match_srcid_en << 23) |
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((src_id & 0xfff) << 8) |
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(wrap << 1) |
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(en << 0));
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nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
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}
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void nlm_cms_endian_byte_swap (uint64_t base, int en)
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{
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nlm_write_cms_reg(base, CMS_MSG_ENDIAN_SWAP, en);
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}
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