348 lines
8.2 KiB
C
348 lines
8.2 KiB
C
/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner module clocks
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_subr.h>
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#include <dev/extres/clk/clk_mux.h>
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#include <dev/extres/clk/clk_gate.h>
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#include "clkdev_if.h"
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#define SCLK_GATING (1 << 31)
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#define CLK_SRC_SEL (0x3 << 24)
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#define CLK_SRC_SEL_SHIFT 24
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#define CLK_RATIO_N (0x3 << 16)
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#define CLK_RATIO_N_SHIFT 16
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#define CLK_RATIO_N_MAX 0x3
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#define CLK_RATIO_M (0xf << 0)
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#define CLK_RATIO_M_SHIFT 0
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#define CLK_RATIO_M_MAX 0xf
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10-mod0-clk", 1 },
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{ NULL, 0 }
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};
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struct aw_modclk_sc {
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device_t clkdev;
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bus_addr_t reg;
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};
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#define MODCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
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#define MODCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
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#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev)
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#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
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static int
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aw_modclk_init(struct clknode *clk, device_t dev)
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{
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struct aw_modclk_sc *sc;
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uint32_t val, index;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(sc);
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MODCLK_READ(sc, &val);
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DEVICE_UNLOCK(sc);
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index = (val & CLK_SRC_SEL) >> CLK_SRC_SEL_SHIFT;
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if (index <= clknode_get_parents_num(clk))
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clknode_init_parent_idx(clk, index);
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else
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clknode_init_parent_idx(clk, 0);
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return (0);
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}
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static int
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aw_modclk_set_mux(struct clknode *clk, int index)
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{
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struct aw_modclk_sc *sc;
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uint32_t val;
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sc = clknode_get_softc(clk);
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if (index < 0 || index >= clknode_get_parents_num(clk))
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return (ERANGE);
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DEVICE_LOCK(sc);
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MODCLK_READ(sc, &val);
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val &= ~CLK_SRC_SEL;
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val |= (index << CLK_SRC_SEL_SHIFT);
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MODCLK_WRITE(sc, val);
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DEVICE_UNLOCK(sc);
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return (0);
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}
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static int
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aw_modclk_set_gate(struct clknode *clk, bool enable)
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{
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struct aw_modclk_sc *sc;
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uint32_t val;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(sc);
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MODCLK_READ(sc, &val);
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if (enable)
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val |= SCLK_GATING;
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else
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val &= ~SCLK_GATING;
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MODCLK_WRITE(sc, val);
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DEVICE_UNLOCK(sc);
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return (0);
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}
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static int
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aw_modclk_recalc_freq(struct clknode *clk, uint64_t *freq)
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{
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struct aw_modclk_sc *sc;
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uint32_t val, m, n;
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sc = clknode_get_softc(clk);
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DEVICE_LOCK(sc);
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MODCLK_READ(sc, &val);
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DEVICE_UNLOCK(sc);
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n = 1 << ((val & CLK_RATIO_N) >> CLK_RATIO_N_SHIFT);
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m = ((val & CLK_RATIO_M) >> CLK_RATIO_M_SHIFT) + 1;
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*freq = *freq / n / m;
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return (0);
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}
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static int
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aw_modclk_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
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int flags, int *stop)
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{
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struct aw_modclk_sc *sc;
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struct clknode *parent_clk, *best_parent;
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const char **parent_names;
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uint32_t val, m, n, src, best_m, best_n, best_src;
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uint64_t cur_freq;
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int64_t best_diff, cur_diff;
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int error;
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sc = clknode_get_softc(clk);
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best_n = best_m = 0;
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best_diff = (int64_t)*fout;
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best_src = 0;
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parent_names = clknode_get_parent_names(clk);
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for (src = 0; src < clknode_get_parents_num(clk); src++) {
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parent_clk = clknode_find_by_name(parent_names[src]);
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if (parent_clk == NULL)
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continue;
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error = clknode_get_freq(parent_clk, &fin);
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if (error != 0)
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continue;
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for (n = 0; n <= CLK_RATIO_N_MAX; n++)
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for (m = 0; m <= CLK_RATIO_M_MAX; m++) {
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cur_freq = fin / (1 << n) / (m + 1);
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cur_diff = (int64_t)*fout - cur_freq;
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if (cur_diff >= 0 && cur_diff < best_diff) {
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best_src = src;
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best_parent = parent_clk;
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best_diff = cur_diff;
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best_m = m;
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best_n = n;
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}
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}
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}
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if (best_diff == (int64_t)*fout)
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return (ERANGE);
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error = clknode_get_freq(best_parent, &fin);
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if (error != 0)
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return (error);
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*fout = fin / (1 << best_n) / (best_m + 1);
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*stop = 1;
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if ((flags & CLK_SET_DRYRUN) != 0)
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return (0);
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error = clknode_set_parent_by_idx(clk, best_src);
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if (error != 0)
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return (error);
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DEVICE_LOCK(sc);
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MODCLK_READ(sc, &val);
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val &= ~(CLK_RATIO_N | CLK_RATIO_M);
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val |= (best_n << CLK_RATIO_N_SHIFT);
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val |= (best_m << CLK_RATIO_M_SHIFT);
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MODCLK_WRITE(sc, val);
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DEVICE_UNLOCK(sc);
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return (0);
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}
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static clknode_method_t aw_modclk_clknode_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, aw_modclk_init),
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CLKNODEMETHOD(clknode_set_gate, aw_modclk_set_gate),
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CLKNODEMETHOD(clknode_set_mux, aw_modclk_set_mux),
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CLKNODEMETHOD(clknode_recalc_freq, aw_modclk_recalc_freq),
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CLKNODEMETHOD(clknode_set_freq, aw_modclk_set_freq),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(aw_modclk_clknode, aw_modclk_clknode_class,
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aw_modclk_clknode_methods, sizeof(struct aw_modclk_sc), clknode_class);
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static int
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aw_modclk_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Allwinner Module Clock");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aw_modclk_attach(device_t dev)
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{
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struct clknode_init_def def;
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struct aw_modclk_sc *sc;
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struct clkdom *clkdom;
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struct clknode *clk;
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clk_t clk_parent;
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bus_addr_t paddr;
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bus_size_t psize;
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phandle_t node;
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int error, ncells, i;
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node = ofw_bus_get_node(dev);
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if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
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device_printf(dev, "cannot parse 'reg' property\n");
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return (ENXIO);
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}
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error = ofw_bus_parse_xref_list_get_length(node, "clocks",
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"#clock-cells", &ncells);
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if (error != 0) {
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device_printf(dev, "cannot get clock count\n");
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return (error);
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}
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clkdom = clkdom_create(dev);
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memset(&def, 0, sizeof(def));
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error = clk_parse_ofw_clk_name(dev, node, &def.name);
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if (error != 0) {
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device_printf(dev, "cannot parse clock name\n");
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error = ENXIO;
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goto fail;
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}
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def.id = 1;
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def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
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for (i = 0; i < ncells; i++) {
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error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
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if (error != 0) {
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device_printf(dev, "cannot get clock %d\n", i);
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goto fail;
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}
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def.parent_names[i] = clk_get_name(clk_parent);
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clk_release(clk_parent);
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}
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def.parent_cnt = ncells;
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clk = clknode_create(clkdom, &aw_modclk_clknode_class, &def);
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if (clk == NULL) {
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device_printf(dev, "cannot create clknode\n");
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error = ENXIO;
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goto fail;
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}
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sc = clknode_get_softc(clk);
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sc->reg = paddr;
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sc->clkdev = device_get_parent(dev);
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clknode_register(clkdom, clk);
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if (clkdom_finit(clkdom) != 0) {
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device_printf(dev, "cannot finalize clkdom initialization\n");
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error = ENXIO;
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goto fail;
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}
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if (bootverbose)
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clkdom_dump(clkdom);
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return (0);
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fail:
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return (error);
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}
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static device_method_t aw_modclk_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, aw_modclk_probe),
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DEVMETHOD(device_attach, aw_modclk_attach),
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DEVMETHOD_END
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};
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static driver_t aw_modclk_driver = {
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"aw_modclk",
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aw_modclk_methods,
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0
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};
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static devclass_t aw_modclk_devclass;
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EARLY_DRIVER_MODULE(aw_modclk, simplebus, aw_modclk_driver,
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aw_modclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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