Submitted by: kib@ Approved by: hselasky (mentor) MFC after: 1 week Sponsored by: Mellanox Technologies
98 lines
2.9 KiB
C
98 lines
2.9 KiB
C
/*-
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* Copyright (c) 2017 Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* $FreeBSD$
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*/
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#ifndef __MLX5_FPGA_CONN_H__
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#define __MLX5_FPGA_CONN_H__
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#include <dev/mlx5/cq.h>
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#include <dev/mlx5/qp.h>
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#include <dev/mlx5/mlx5_fpga/core.h>
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#include <dev/mlx5/mlx5_fpga/sdk.h>
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#include <dev/mlx5/mlx5_core/wq.h>
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#include <linux/interrupt.h>
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struct mlx5_fpga_conn {
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struct mlx5_fpga_device *fdev;
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void (*recv_cb)(void *cb_arg, struct mlx5_fpga_dma_buf *buf);
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void *cb_arg;
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/* FPGA QP */
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u32 fpga_qpc[MLX5_ST_SZ_DW(fpga_qpc)];
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u32 fpga_qpn;
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/* CQ */
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struct {
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struct mlx5_cqwq wq;
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struct mlx5_frag_wq_ctrl wq_ctrl;
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struct mlx5_core_cq mcq;
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struct tasklet_struct tasklet;
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} cq;
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/* QP */
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struct {
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bool active;
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int sgid_index;
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struct mlx5_wq_qp wq;
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struct mlx5_wq_ctrl wq_ctrl;
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struct mlx5_core_qp mqp;
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struct {
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spinlock_t lock; /* Protects all SQ state */
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unsigned int pc;
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unsigned int cc;
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unsigned int size;
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struct mlx5_fpga_dma_buf **bufs;
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struct list_head backlog;
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} sq;
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struct {
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unsigned int pc;
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unsigned int cc;
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unsigned int size;
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struct mlx5_fpga_dma_buf **bufs;
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} rq;
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} qp;
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};
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int mlx5_fpga_conn_device_init(struct mlx5_fpga_device *fdev);
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void mlx5_fpga_conn_device_cleanup(struct mlx5_fpga_device *fdev);
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struct mlx5_fpga_conn *
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mlx5_fpga_conn_create(struct mlx5_fpga_device *fdev,
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struct mlx5_fpga_conn_attr *attr,
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enum mlx5_ifc_fpga_qp_type qp_type);
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void mlx5_fpga_conn_destroy(struct mlx5_fpga_conn *conn);
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int mlx5_fpga_conn_send(struct mlx5_fpga_conn *conn,
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struct mlx5_fpga_dma_buf *buf);
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#endif /* __MLX5_FPGA_CONN_H__ */
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