02c1dc3bbc
interrupts are masked, and EOI is sent iff the corresponding ISR bit is set in the local apic. If the CPU cannot obtain the interrupt service lock (currently the global kernel lock) the interrupt is forwarded to the CPU holding that lock. Clock interrupts now have higher priority than other slow interrupts.
529 lines
14 KiB
C
529 lines
14 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)isa.c 7.2 (Berkeley) 5/13/91
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* $Id: intr_machdep.c,v 1.8 1998/02/09 06:08:30 eivind Exp $
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*/
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#include "opt_auto_eoi.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/syslog.h>
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#include <machine/ipl.h>
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#include <machine/md_var.h>
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#include <machine/segments.h>
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#if defined(APIC_IO)
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#include <machine/smp.h>
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#include <machine/smptests.h> /** FAST_HI */
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#endif /* APIC_IO */
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#include <i386/isa/isa_device.h>
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#ifdef PC98
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#include <pc98/pc98/pc98.h>
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#include <pc98/pc98/pc98_machdep.h>
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#include <pc98/pc98/epsonio.h>
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#else
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#include <i386/isa/isa.h>
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#endif
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#include <i386/isa/icu.h>
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#include "vector.h"
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#include <i386/isa/intr_machdep.h>
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#include <sys/interrupt.h>
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/* XXX should be in suitable include files */
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#ifdef PC98
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#define ICU_IMR_OFFSET 2 /* IO_ICU{1,2} + 2 */
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#define ICU_SLAVEID 7
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#else
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#define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */
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#define ICU_SLAVEID 2
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#endif
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#ifdef APIC_IO
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/*
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* This is to accommodate "mixed-mode" programming for
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* motherboards that don't connect the 8254 to the IO APIC.
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*/
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#define AUTO_EOI_1
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#endif
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u_long *intr_countp[ICU_LEN];
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inthand2_t *intr_handler[ICU_LEN];
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u_int intr_mask[ICU_LEN];
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static u_int* intr_mptr[ICU_LEN];
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int intr_unit[ICU_LEN];
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static inthand_t *fastintr[ICU_LEN] = {
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&IDTVEC(fastintr0), &IDTVEC(fastintr1),
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&IDTVEC(fastintr2), &IDTVEC(fastintr3),
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&IDTVEC(fastintr4), &IDTVEC(fastintr5),
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&IDTVEC(fastintr6), &IDTVEC(fastintr7),
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&IDTVEC(fastintr8), &IDTVEC(fastintr9),
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&IDTVEC(fastintr10), &IDTVEC(fastintr11),
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&IDTVEC(fastintr12), &IDTVEC(fastintr13),
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&IDTVEC(fastintr14), &IDTVEC(fastintr15)
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#if defined(APIC_IO)
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, &IDTVEC(fastintr16), &IDTVEC(fastintr17),
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&IDTVEC(fastintr18), &IDTVEC(fastintr19),
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&IDTVEC(fastintr20), &IDTVEC(fastintr21),
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&IDTVEC(fastintr22), &IDTVEC(fastintr23)
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#endif /* APIC_IO */
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};
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static inthand_t *slowintr[ICU_LEN] = {
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&IDTVEC(intr0), &IDTVEC(intr1), &IDTVEC(intr2), &IDTVEC(intr3),
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&IDTVEC(intr4), &IDTVEC(intr5), &IDTVEC(intr6), &IDTVEC(intr7),
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&IDTVEC(intr8), &IDTVEC(intr9), &IDTVEC(intr10), &IDTVEC(intr11),
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&IDTVEC(intr12), &IDTVEC(intr13), &IDTVEC(intr14), &IDTVEC(intr15)
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#if defined(APIC_IO)
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, &IDTVEC(intr16), &IDTVEC(intr17), &IDTVEC(intr18), &IDTVEC(intr19),
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&IDTVEC(intr20), &IDTVEC(intr21), &IDTVEC(intr22), &IDTVEC(intr23)
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#endif /* APIC_IO */
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};
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static inthand2_t isa_strayintr;
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#ifdef PC98
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#define NMI_PARITY 0x04
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#define NMI_EPARITY 0x02
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#else
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#define NMI_PARITY (1 << 7)
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#define NMI_IOCHAN (1 << 6)
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#define ENMI_WATCHDOG (1 << 7)
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#define ENMI_BUSTIMER (1 << 6)
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#define ENMI_IOSTATUS (1 << 5)
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#endif
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/*
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* Handle a NMI, possibly a machine check.
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* return true to panic system, false to ignore.
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*/
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int
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isa_nmi(cd)
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int cd;
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{
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#ifdef PC98
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int port = inb(0x33);
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if (epson_machine_id == 0x20)
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epson_outb(0xc16, epson_inb(0xc16) | 0x1);
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if (port & NMI_PARITY) {
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panic("BASE RAM parity error, likely hardware failure.");
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} else if (port & NMI_EPARITY) {
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panic("EXTENDED RAM parity error, likely hardware failure.");
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} else {
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printf("\nNMI Resume ??\n");
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return(0);
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}
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#else /* IBM-PC */
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int isa_port = inb(0x61);
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int eisa_port = inb(0x461);
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if (isa_port & NMI_PARITY)
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panic("RAM parity error, likely hardware failure.");
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if (isa_port & NMI_IOCHAN)
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panic("I/O channel check, likely hardware failure.");
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/*
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* On a real EISA machine, this will never happen. However it can
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* happen on ISA machines which implement XT style floating point
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* error handling (very rare). Save them from a meaningless panic.
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*/
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if (eisa_port == 0xff)
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return(0);
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if (eisa_port & ENMI_WATCHDOG)
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panic("EISA watchdog timer expired, likely hardware failure.");
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if (eisa_port & ENMI_BUSTIMER)
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panic("EISA bus timeout, likely hardware failure.");
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if (eisa_port & ENMI_IOSTATUS)
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panic("EISA I/O port status error.");
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printf("\nNMI ISA %x, EISA %x\n", isa_port, eisa_port);
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return(0);
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#endif
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}
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/*
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* Fill in default interrupt table (in case of spuruious interrupt
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* during configuration of kernel, setup interrupt control unit
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*/
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void
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isa_defaultirq()
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{
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int i;
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/* icu vectors */
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for (i = 0; i < ICU_LEN; i++)
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icu_unset(i, (inthand2_t *)NULL);
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/* initialize 8259's */
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outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU1+ICU_IMR_OFFSET, NRSVIDT); /* starting at this vector index */
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outb(IO_ICU1+ICU_IMR_OFFSET, IRQ_SLAVE); /* slave on line 7 */
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#ifdef PC98
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#ifdef AUTO_EOI_1
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outb(IO_ICU1+ICU_IMR_OFFSET, 0x1f); /* (master) auto EOI, 8086 mode */
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#else
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outb(IO_ICU1+ICU_IMR_OFFSET, 0x1d); /* (master) 8086 mode */
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#endif
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#else /* IBM-PC */
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#ifdef AUTO_EOI_1
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outb(IO_ICU1+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU1+ICU_IMR_OFFSET, 1); /* 8086 mode */
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#endif
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#endif /* PC98 */
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outb(IO_ICU1+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
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outb(IO_ICU1, 0x0a); /* default to IRR on read */
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#ifndef PC98
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outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
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#endif /* !PC98 */
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outb(IO_ICU2, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU2+ICU_IMR_OFFSET, NRSVIDT+8); /* staring at this vector index */
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outb(IO_ICU2+ICU_IMR_OFFSET, ICU_SLAVEID); /* my slave id is 7 */
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#ifdef PC98
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outb(IO_ICU2+ICU_IMR_OFFSET,9); /* 8086 mode */
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#else /* IBM-PC */
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#ifdef AUTO_EOI_2
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outb(IO_ICU2+ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU2+ICU_IMR_OFFSET,1); /* 8086 mode */
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#endif
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#endif /* PC98 */
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outb(IO_ICU2+ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */
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outb(IO_ICU2, 0x0a); /* default to IRR on read */
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}
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/*
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* Caught a stray interrupt, notify
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*/
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static void
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isa_strayintr(d)
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int d;
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{
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/* DON'T BOTHER FOR NOW! */
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/* for some reason, we get bursts of intr #7, even if not enabled! */
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/*
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* Well the reason you got bursts of intr #7 is because someone
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* raised an interrupt line and dropped it before the 8259 could
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* prioritize it. This is documented in the intel data book. This
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* means you have BAD hardware! I have changed this so that only
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* the first 5 get logged, then it quits logging them, and puts
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* out a special message. rgrimes 3/25/1993
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*/
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/*
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* XXX TODO print a different message for #7 if it is for a
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* glitch. Glitches can be distinguished from real #7's by
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* testing that the in-service bit is _not_ set. The test
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* must be done before sending an EOI so it can't be done if
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* we are using AUTO_EOI_1.
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*/
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if (intrcnt[NR_DEVICES + d] <= 5)
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log(LOG_ERR, "stray irq %d\n", d);
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if (intrcnt[NR_DEVICES + d] == 5)
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log(LOG_CRIT,
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"too many stray irq %d's; not logging any more\n", d);
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}
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/*
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* Return nonzero if a (masked) irq is pending for a given device.
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*/
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#if defined(APIC_IO)
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int
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isa_irq_pending(dvp)
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struct isa_device *dvp;
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{
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#ifdef FAST_HI
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/* XXX not quite right for >1 IO APIC yet */
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if (dvp->id_ri_flags & RI_FAST)
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/* read APIC IRR containing the FAST INTerrupts */
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return ((lapic.irr3 & 0x00ffffff)
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& (u_int32_t)dvp->id_irq) ? 1 : 0;
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else
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#endif /* FAST_HI */
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/* read APIC IRR containing the SLOW INTerrupts */
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return ((lapic.irr1 & 0x00ffffff)
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& (u_int32_t)dvp->id_irq) ? 1 : 0;
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}
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/*
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* an 8259 specific routine,
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* for use by boot probes in certain device drivers.
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*/
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int
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icu_irq_pending(dvp)
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struct isa_device *dvp;
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{
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unsigned id_irq;
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id_irq = dvp->id_irq;
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if (id_irq & 0xff)
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return (inb(IO_ICU1) & id_irq);
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return (inb(IO_ICU2) & (id_irq >> 8));
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}
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#else /* APIC_IO */
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int
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isa_irq_pending(dvp)
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struct isa_device *dvp;
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{
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unsigned id_irq;
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id_irq = dvp->id_irq;
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if (id_irq & 0xff)
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return (inb(IO_ICU1) & id_irq);
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return (inb(IO_ICU2) & (id_irq >> 8));
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}
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#endif /* APIC_IO */
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int
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update_intr_masks(void)
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{
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int intr, n=0;
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u_int mask,*maskptr;
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for (intr=0; intr < ICU_LEN; intr ++) {
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#if defined(APIC_IO)
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/* no 8259 SLAVE to ignore */
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#else
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if (intr==ICU_SLAVEID) continue; /* ignore 8259 SLAVE output */
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#endif /* APIC_IO */
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maskptr = intr_mptr[intr];
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if (!maskptr) continue;
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*maskptr |= 1 << intr;
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mask = *maskptr;
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if (mask != intr_mask[intr]) {
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#if 0
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printf ("intr_mask[%2d] old=%08x new=%08x ptr=%p.\n",
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intr, intr_mask[intr], mask, maskptr);
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#endif
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intr_mask[intr]=mask;
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n++;
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}
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}
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return (n);
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}
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/*
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* The find_device_id function is only required because of the way the
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* device names are currently stored for reporting in systat or vmstat.
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* In fact, those programs should be modified to use the sysctl interface
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* to obtain a list of driver names by traversing intreclist_head[irq].
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*/
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static int
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find_device_id(int irq)
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{
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char buf[16];
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char *cp;
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int free_id, id;
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sprintf(buf, "pci irq%d", irq);
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cp = intrnames;
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/* default to 0, which corresponds to clk0 */
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free_id = 0;
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for (id = 0; id < NR_DEVICES; id++) {
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if (strcmp(cp, buf) == 0)
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return (id);
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if (free_id == 0 && strcmp(cp, "pci irqnn") == 0)
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free_id = id;
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while (*cp++ != '\0');
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}
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#if 0
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if (free_id == 0) {
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/*
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* All pci irq counters are in use, perhaps because config
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* is old so there aren't any. Abuse the clk0 counter.
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*/
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printf("\tcounting shared irq%d as clk0 irq\n", irq);
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}
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#endif
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return (free_id);
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}
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void
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update_intrname(int intr, int device_id)
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{
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char *cp;
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int id;
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if (device_id == -1)
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device_id = find_device_id(intr);
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if ((u_int)device_id >= NR_DEVICES)
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return;
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intr_countp[intr] = &intrcnt[device_id];
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for (cp = intrnames, id = 0; id <= device_id; id++)
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while (*cp++ != '\0')
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;
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if (cp > eintrnames)
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return;
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if (intr < 10) {
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cp[-3] = intr + '0';
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cp[-2] = ' ';
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} else if (intr < 20) {
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cp[-3] = '1';
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cp[-2] = intr - 10 + '0';
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} else {
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cp[-3] = '2';
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cp[-2] = intr - 20 + '0';
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}
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}
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int
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icu_setup(int intr, inthand2_t *handler, void *arg, u_int *maskptr, int flags)
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{
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#ifdef FAST_HI
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int select; /* the select register is 8 bits */
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int vector;
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u_int32_t value; /* the window register is 32 bits */
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#endif /* FAST_HI */
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u_long ef;
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u_int mask = (maskptr ? *maskptr : 0);
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#if defined(APIC_IO)
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if ((u_int)intr >= ICU_LEN) /* no 8259 SLAVE to ignore */
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#else
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if ((u_int)intr >= ICU_LEN || intr == ICU_SLAVEID)
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#endif /* APIC_IO */
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if (intr_handler[intr] != isa_strayintr)
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return (EBUSY);
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ef = read_eflags();
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disable_intr();
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intr_handler[intr] = handler;
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intr_mptr[intr] = maskptr;
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intr_mask[intr] = mask | (1 << intr);
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intr_unit[intr] = (int) arg;
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#ifdef FAST_HI
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if (flags & INTR_FAST) {
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vector = TPR_FAST_INTS + intr;
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setidt(vector, fastintr[intr],
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SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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}
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else {
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vector = TPR_SLOW_INTS + intr;
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#ifdef APIC_INTR_REORDER
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#ifdef APIC_INTR_HIGHPRI_CLOCK
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/* XXX: Hack (kludge?) for more accurate clock. */
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if (intr == 0 || intr == 8) {
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vector = TPR_FAST_INTS + intr;
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}
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#endif
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#endif
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setidt(vector, slowintr[intr],
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SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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}
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#ifdef APIC_INTR_REORDER
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set_lapic_isrloc(intr, vector);
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#endif
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/*
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* XXX MULTIPLE_IOAPICSXXX
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* Reprogram the vector in the IO APIC.
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*/
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select = (intr * 2) + IOAPIC_REDTBL0;
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value = io_apic_read(0, select) & ~IOART_INTVEC;
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io_apic_write(0, select, value | vector);
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#else
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setidt(ICU_OFFSET + intr,
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flags & INTR_FAST ? fastintr[intr] : slowintr[intr],
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SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
|
|
#endif /* FAST_HI */
|
|
INTREN(1 << intr);
|
|
MPINTR_UNLOCK();
|
|
write_eflags(ef);
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
register_imask(dvp, mask)
|
|
struct isa_device *dvp;
|
|
u_int mask;
|
|
{
|
|
if (dvp->id_alive && dvp->id_irq) {
|
|
int intr;
|
|
|
|
intr = ffs(dvp->id_irq) - 1;
|
|
intr_mask[intr] = mask | (1 <<intr);
|
|
}
|
|
(void) update_intr_masks();
|
|
}
|
|
|
|
int
|
|
icu_unset(intr, handler)
|
|
int intr;
|
|
inthand2_t *handler;
|
|
{
|
|
u_long ef;
|
|
|
|
if ((u_int)intr >= ICU_LEN || handler != intr_handler[intr])
|
|
return (EINVAL);
|
|
|
|
INTRDIS(1 << intr);
|
|
ef = read_eflags();
|
|
disable_intr();
|
|
intr_countp[intr] = &intrcnt[NR_DEVICES + intr];
|
|
intr_handler[intr] = isa_strayintr;
|
|
intr_mptr[intr] = NULL;
|
|
intr_mask[intr] = HWI_MASK | SWI_MASK;
|
|
intr_unit[intr] = intr;
|
|
#ifdef FAST_HI_XXX
|
|
/* XXX how do I re-create dvp here? */
|
|
setidt(flags & INTR_FAST ? TPR_FAST_INTS + intr : TPR_SLOW_INTS + intr,
|
|
slowintr[intr], SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
|
|
#else /* FAST_HI */
|
|
#ifdef APIC_INTR_REORDER
|
|
set_lapic_isrloc(intr, ICU_OFFSET + intr);
|
|
#endif
|
|
setidt(ICU_OFFSET + intr, slowintr[intr], SDT_SYS386IGT, SEL_KPL,
|
|
GSEL(GCODE_SEL, SEL_KPL));
|
|
#endif /* FAST_HI */
|
|
MPINTR_UNLOCK();
|
|
write_eflags(ef);
|
|
return (0);
|
|
}
|