5e4e1d4995
and the functionality it provided into arm/exception.S. Rename the main irq handling routine from arm_handler_execute() to arm_irq_handler() to make it more congruent with how other exception handlers are named, and also update its signature to reflect what has long been reality: it is passed just a trapframe pointer, no interrupt number argument.
43 lines
1.1 KiB
Plaintext
43 lines
1.1 KiB
Plaintext
# $FreeBSD$
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#
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# The Marvell CPU cores
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# - Compliant with V5TE architecture
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# - Super scalar dual issue CPU
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# - Big/Little Endian
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# - MMU/MPU
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# - L1 Cache: Supports streaming and write allocate
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# - Variable pipeline stages
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# - Out-of-order execution
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# - Branch Prediction
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# - JTAG/ICE
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# - Vector Floating Point (VFP) unit
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#
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arm/arm/bus_space_generic.c standard
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arm/arm/cpufunc_asm_arm10.S standard
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arm/arm/cpufunc_asm_arm11.S standard
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arm/arm/cpufunc_asm_armv5.S standard
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arm/arm/cpufunc_asm_armv5_ec.S standard
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arm/arm/cpufunc_asm_armv7.S standard
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arm/arm/cpufunc_asm_sheeva.S standard
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arm/arm/cpufunc_asm_pj4b.S standard
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arm/mv/bus_space.c standard
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arm/mv/gpio.c standard
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arm/mv/mv_common.c standard
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arm/mv/mv_localbus.c standard
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arm/mv/mv_machdep.c standard
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arm/mv/mv_pci.c optional pci
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arm/mv/mv_sata.c optional ata | atamvsata
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arm/mv/mv_ts.c standard
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arm/mv/timer.c standard
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arm/mv/twsi.c optional iicbus
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dev/cesa/cesa.c optional cesa
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dev/mge/if_mge.c optional mge
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dev/nand/nfc_mv.c optional nand
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dev/mvs/mvs_soc.c optional mvs
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dev/uart/uart_dev_ns8250.c optional uart
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dev/usb/controller/ehci_mv.c optional ehci
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kern/kern_clocksource.c standard
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