450 lines
12 KiB
C
450 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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/*
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* Written using information gleaned from the
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* NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <dev/agp/agppriv.h>
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#include <dev/agp/agpreg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <vm/vm.h>
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#include <vm/vm_object.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#define NVIDIA_VENDORID 0x10de
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#define NVIDIA_DEVICEID_NFORCE 0x01a4
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#define NVIDIA_DEVICEID_NFORCE2 0x01e0
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struct agp_nvidia_softc {
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struct agp_softc agp;
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u_int32_t initial_aperture; /* aperture size at startup */
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struct agp_gatt * gatt;
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device_t dev; /* AGP Controller */
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device_t mc1_dev; /* Memory Controller */
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device_t mc2_dev; /* Memory Controller */
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device_t bdev; /* Bridge */
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u_int32_t wbc_mask;
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int num_dirs;
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int num_active_entries;
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off_t pg_offset;
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};
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static const char *agp_nvidia_match(device_t dev);
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static int agp_nvidia_probe(device_t);
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static int agp_nvidia_attach(device_t);
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static int agp_nvidia_detach(device_t);
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static u_int32_t agp_nvidia_get_aperture(device_t);
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static int agp_nvidia_set_aperture(device_t, u_int32_t);
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static int agp_nvidia_bind_page(device_t, vm_offset_t, vm_offset_t);
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static int agp_nvidia_unbind_page(device_t, vm_offset_t);
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static int nvidia_init_iorr(u_int32_t, u_int32_t);
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static const char *
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agp_nvidia_match (device_t dev)
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{
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if (pci_get_class(dev) != PCIC_BRIDGE ||
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pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
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pci_get_vendor(dev) != NVIDIA_VENDORID)
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return (NULL);
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switch (pci_get_device(dev)) {
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case NVIDIA_DEVICEID_NFORCE:
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return ("NVIDIA nForce AGP Controller");
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case NVIDIA_DEVICEID_NFORCE2:
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return ("NVIDIA nForce2 AGP Controller");
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}
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return (NULL);
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}
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static int
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agp_nvidia_probe (device_t dev)
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{
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const char *desc;
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if (resource_disabled("agp", device_get_unit(dev)))
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return (ENXIO);
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desc = agp_nvidia_match(dev);
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if (desc) {
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device_set_desc(dev, desc);
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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agp_nvidia_attach (device_t dev)
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{
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struct agp_nvidia_softc *sc = device_get_softc(dev);
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struct agp_gatt *gatt;
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u_int32_t apbase;
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u_int32_t aplimit;
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u_int32_t temp;
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int size;
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int i;
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int error;
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switch (pci_get_device(dev)) {
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case NVIDIA_DEVICEID_NFORCE:
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sc->wbc_mask = 0x00010000;
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break;
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case NVIDIA_DEVICEID_NFORCE2:
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sc->wbc_mask = 0x80000000;
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break;
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default:
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device_printf(dev, "Bad chip id\n");
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return (ENODEV);
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}
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/* AGP Controller */
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sc->dev = dev;
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/* Memory Controller 1 */
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sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
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if (sc->mc1_dev == NULL) {
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device_printf(dev,
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"Unable to find NVIDIA Memory Controller 1.\n");
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return (ENODEV);
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}
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/* Memory Controller 2 */
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sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
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if (sc->mc2_dev == NULL) {
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device_printf(dev,
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"Unable to find NVIDIA Memory Controller 2.\n");
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return (ENODEV);
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}
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/* AGP Host to PCI Bridge */
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sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
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if (sc->bdev == NULL) {
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device_printf(dev,
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"Unable to find NVIDIA AGP Host to PCI Bridge.\n");
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return (ENODEV);
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}
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error = agp_generic_attach(dev);
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if (error)
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return (error);
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sc->initial_aperture = AGP_GET_APERTURE(dev);
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for (;;) {
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gatt = agp_alloc_gatt(dev);
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if (gatt)
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break;
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/*
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* Probably contigmalloc failure. Try reducing the
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* aperture so that the gatt size reduces.
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*/
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if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
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goto fail;
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}
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sc->gatt = gatt;
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apbase = rman_get_start(sc->agp.as_aperture);
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aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
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pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
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pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
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pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
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pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
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error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
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if (error) {
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device_printf(dev, "Failed to setup IORRs\n");
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goto fail;
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}
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/* directory size is 64k */
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size = AGP_GET_APERTURE(dev) / 1024 / 1024;
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sc->num_dirs = size / 64;
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sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
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sc->pg_offset = 0;
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if (sc->num_dirs == 0) {
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sc->num_dirs = 1;
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sc->num_active_entries /= (64 / size);
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sc->pg_offset = rounddown2(apbase & (64 * 1024 * 1024 - 1),
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AGP_GET_APERTURE(dev)) / PAGE_SIZE;
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}
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/* (G)ATT Base Address */
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for (i = 0; i < 8; i++) {
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pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
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(sc->gatt->ag_physical +
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(i % sc->num_dirs) * 64 * 1024) | 1, 4);
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}
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/* GTLB Control */
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temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
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pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
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/* GART Control */
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temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
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pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
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return (0);
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fail:
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agp_generic_detach(dev);
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return (ENOMEM);
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}
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static int
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agp_nvidia_detach (device_t dev)
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{
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struct agp_nvidia_softc *sc = device_get_softc(dev);
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u_int32_t temp;
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agp_free_cdev(dev);
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/* GART Control */
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temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
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pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
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/* GTLB Control */
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temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
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pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
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/* Put the aperture back the way it started. */
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AGP_SET_APERTURE(dev, sc->initial_aperture);
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/* restore iorr for previous aperture size */
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nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
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sc->initial_aperture);
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agp_free_gatt(sc->gatt);
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agp_free_res(dev);
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return (0);
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}
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static u_int32_t
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agp_nvidia_get_aperture(device_t dev)
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{
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switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) {
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case 0: return (512 * 1024 * 1024);
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case 8: return (256 * 1024 * 1024);
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case 12: return (128 * 1024 * 1024);
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case 14: return (64 * 1024 * 1024);
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case 15: return (32 * 1024 * 1024);
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default:
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device_printf(dev, "Invalid aperture setting 0x%x\n",
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pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1));
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return 0;
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}
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}
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static int
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agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
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{
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u_int8_t val;
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u_int8_t key;
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switch (aperture) {
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case (512 * 1024 * 1024): key = 0; break;
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case (256 * 1024 * 1024): key = 8; break;
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case (128 * 1024 * 1024): key = 12; break;
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case (64 * 1024 * 1024): key = 14; break;
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case (32 * 1024 * 1024): key = 15; break;
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default:
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device_printf(dev, "Invalid aperture size (%dMb)\n",
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aperture / 1024 / 1024);
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return (EINVAL);
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}
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val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
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pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
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return (0);
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}
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static int
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agp_nvidia_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
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{
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struct agp_nvidia_softc *sc = device_get_softc(dev);
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u_int32_t index;
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if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return (EINVAL);
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index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
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sc->gatt->ag_virtual[index] = physical | 1;
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return (0);
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}
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static int
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agp_nvidia_unbind_page(device_t dev, vm_offset_t offset)
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{
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struct agp_nvidia_softc *sc = device_get_softc(dev);
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u_int32_t index;
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if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return (EINVAL);
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index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
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sc->gatt->ag_virtual[index] = 0;
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return (0);
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}
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static void
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agp_nvidia_flush_tlb (device_t dev)
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{
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struct agp_nvidia_softc *sc;
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u_int32_t wbc_reg;
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volatile u_int32_t *ag_virtual;
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int i, pages;
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sc = (struct agp_nvidia_softc *)device_get_softc(dev);
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if (sc->wbc_mask) {
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wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
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wbc_reg |= sc->wbc_mask;
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pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
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/* Wait no more than 3 seconds. */
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for (i = 0; i < 3000; i++) {
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wbc_reg = pci_read_config(sc->mc1_dev,
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AGP_NVIDIA_1_WBC, 4);
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if ((sc->wbc_mask & wbc_reg) == 0)
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break;
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else
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DELAY(1000);
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}
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if (i == 3000)
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device_printf(dev,
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"TLB flush took more than 3 seconds.\n");
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}
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ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual;
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/* Flush TLB entries. */
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pages = sc->gatt->ag_entries * sizeof(u_int32_t) / PAGE_SIZE;
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for(i = 0; i < pages; i++)
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(void)ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
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for(i = 0; i < pages; i++)
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(void)ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
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}
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#define SYSCFG 0xC0010010
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#define IORR_BASE0 0xC0010016
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#define IORR_MASK0 0xC0010017
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#define AMD_K7_NUM_IORR 2
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static int
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nvidia_init_iorr(u_int32_t addr, u_int32_t size)
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{
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quad_t base, mask, sys;
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u_int32_t iorr_addr, free_iorr_addr;
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/* Find the iorr that is already used for the addr */
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/* If not found, determine the uppermost available iorr */
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free_iorr_addr = AMD_K7_NUM_IORR;
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for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
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base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
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mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
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if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
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break;
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if ((mask & 0x00000800ULL) == 0)
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free_iorr_addr = iorr_addr;
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}
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if (iorr_addr >= AMD_K7_NUM_IORR) {
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iorr_addr = free_iorr_addr;
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if (iorr_addr >= AMD_K7_NUM_IORR)
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return (EINVAL);
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}
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base = (addr & ~0xfff) | 0x18;
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mask = (0xfULL << 32) | rounddown2(0xfffff000, size) | 0x800;
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wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
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wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
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sys = rdmsr(SYSCFG);
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sys |= 0x00100000ULL;
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wrmsr(SYSCFG, sys);
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return (0);
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}
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static device_method_t agp_nvidia_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, agp_nvidia_probe),
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DEVMETHOD(device_attach, agp_nvidia_attach),
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DEVMETHOD(device_detach, agp_nvidia_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* AGP interface */
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DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
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DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
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DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
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DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
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DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
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DEVMETHOD(agp_enable, agp_generic_enable),
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DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
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DEVMETHOD(agp_free_memory, agp_generic_free_memory),
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DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
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DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
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{ 0, 0 }
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};
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static driver_t agp_nvidia_driver = {
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"agp",
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agp_nvidia_methods,
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sizeof(struct agp_nvidia_softc),
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};
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DRIVER_MODULE(agp_nvidia, hostb, agp_nvidia_driver, 0, 0);
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MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
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MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
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