764 lines
16 KiB
C
764 lines
16 KiB
C
/*-
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* Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Cadence Quad SPI Flash Controller driver.
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* 4B-addressing mode supported only.
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*/
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#include <sys/cdefs.h>
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/lock.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <geom/geom_disk.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/flash/cqspi.h>
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#include <dev/flash/mx25lreg.h>
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#include <dev/xdma/xdma.h>
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#include "qspi_if.h"
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#define CQSPI_DEBUG
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#undef CQSPI_DEBUG
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#ifdef CQSPI_DEBUG
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#define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
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#else
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#define dprintf(fmt, ...)
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#endif
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#define CQSPI_SECTORSIZE 512
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#define TX_QUEUE_SIZE 16
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#define RX_QUEUE_SIZE 16
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#define READ4(_sc, _reg) bus_read_4((_sc)->res[0], _reg)
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#define READ2(_sc, _reg) bus_read_2((_sc)->res[0], _reg)
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#define READ1(_sc, _reg) bus_read_1((_sc)->res[0], _reg)
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#define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val)
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#define WRITE2(_sc, _reg, _val) bus_write_2((_sc)->res[0], _reg, _val)
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#define WRITE1(_sc, _reg, _val) bus_write_1((_sc)->res[0], _reg, _val)
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#define READ_DATA_4(_sc, _reg) bus_read_4((_sc)->res[1], _reg)
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#define READ_DATA_1(_sc, _reg) bus_read_1((_sc)->res[1], _reg)
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#define WRITE_DATA_4(_sc, _reg, _val) bus_write_4((_sc)->res[1], _reg, _val)
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#define WRITE_DATA_1(_sc, _reg, _val) bus_write_1((_sc)->res[1], _reg, _val)
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struct cqspi_softc {
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device_t dev;
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struct resource *res[3];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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void *ih;
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uint8_t read_op_done;
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uint8_t write_op_done;
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uint32_t fifo_depth;
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uint32_t fifo_width;
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uint32_t trigger_address;
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uint32_t sram_phys;
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/* xDMA */
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xdma_controller_t *xdma_tx;
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xdma_channel_t *xchan_tx;
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void *ih_tx;
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xdma_controller_t *xdma_rx;
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xdma_channel_t *xchan_rx;
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void *ih_rx;
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struct intr_config_hook config_intrhook;
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struct mtx sc_mtx;
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};
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#define CQSPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define CQSPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define CQSPI_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
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"cqspi", MTX_DEF)
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#define CQSPI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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#define CQSPI_ASSERT_LOCKED(_sc) \
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mtx_assert(&_sc->sc_mtx, MA_OWNED);
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#define CQSPI_ASSERT_UNLOCKED(_sc) \
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mtx_assert(&_sc->sc_mtx, MA_NOTOWNED);
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static struct resource_spec cqspi_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_MEMORY, 1, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct ofw_compat_data compat_data[] = {
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{ "cdns,qspi-nor", 1 },
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{ NULL, 0 },
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};
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static void
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cqspi_intr(void *arg)
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{
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struct cqspi_softc *sc;
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uint32_t pending;
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sc = arg;
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pending = READ4(sc, CQSPI_IRQSTAT);
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dprintf("%s: IRQSTAT %x\n", __func__, pending);
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if (pending & (IRQMASK_INDOPDONE | IRQMASK_INDXFRLVL |
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IRQMASK_INDSRAMFULL)) {
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/* TODO: PIO operation done */
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}
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WRITE4(sc, CQSPI_IRQSTAT, pending);
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}
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static int
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cqspi_xdma_tx_intr(void *arg, xdma_transfer_status_t *status)
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{
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struct xdma_transfer_status st;
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struct cqspi_softc *sc;
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struct bio *bp;
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int ret;
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int deq;
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sc = arg;
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dprintf("%s\n", __func__);
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deq = 0;
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while (1) {
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ret = xdma_dequeue_bio(sc->xchan_tx, &bp, &st);
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if (ret != 0) {
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break;
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}
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sc->write_op_done = 1;
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deq++;
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}
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if (deq > 1)
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device_printf(sc->dev,
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"Warning: more than 1 tx bio dequeued\n");
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wakeup(&sc->xdma_tx);
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return (0);
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}
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static int
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cqspi_xdma_rx_intr(void *arg, xdma_transfer_status_t *status)
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{
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struct xdma_transfer_status st;
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struct cqspi_softc *sc;
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struct bio *bp;
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int ret;
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int deq;
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sc = arg;
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dprintf("%s\n", __func__);
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deq = 0;
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while (1) {
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ret = xdma_dequeue_bio(sc->xchan_rx, &bp, &st);
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if (ret != 0) {
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break;
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}
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sc->read_op_done = 1;
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deq++;
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}
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if (deq > 1)
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device_printf(sc->dev,
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"Warning: more than 1 rx bio dequeued\n");
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wakeup(&sc->xdma_rx);
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return (0);
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}
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static int
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cqspi_wait_for_completion(struct cqspi_softc *sc)
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{
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int timeout;
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int i;
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timeout = 10000;
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for (i = timeout; i > 0; i--) {
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if ((READ4(sc, CQSPI_FLASHCMD) & FLASHCMD_CMDEXECSTAT) == 0) {
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break;
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}
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}
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if (i == 0) {
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device_printf(sc->dev, "%s: cmd timed out: %x\n",
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__func__, READ4(sc, CQSPI_FLASHCMD));
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return (-1);
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}
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return (0);
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}
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static int
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cqspi_cmd_write_addr(struct cqspi_softc *sc, uint8_t cmd,
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uint32_t addr, uint32_t len)
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{
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uint32_t reg;
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int ret;
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dprintf("%s: %x\n", __func__, cmd);
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WRITE4(sc, CQSPI_FLASHCMDADDR, addr);
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reg = (cmd << FLASHCMD_CMDOPCODE_S);
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reg |= (FLASHCMD_ENCMDADDR);
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reg |= ((len - 1) << FLASHCMD_NUMADDRBYTES_S);
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WRITE4(sc, CQSPI_FLASHCMD, reg);
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reg |= FLASHCMD_EXECCMD;
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WRITE4(sc, CQSPI_FLASHCMD, reg);
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ret = cqspi_wait_for_completion(sc);
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return (ret);
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}
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static int
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cqspi_cmd_write(struct cqspi_softc *sc, uint8_t cmd,
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uint8_t *addr, uint32_t len)
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{
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uint32_t reg;
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int ret;
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reg = (cmd << FLASHCMD_CMDOPCODE_S);
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WRITE4(sc, CQSPI_FLASHCMD, reg);
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reg |= FLASHCMD_EXECCMD;
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WRITE4(sc, CQSPI_FLASHCMD, reg);
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ret = cqspi_wait_for_completion(sc);
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return (ret);
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}
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static int
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cqspi_cmd_read(struct cqspi_softc *sc, uint8_t cmd,
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uint8_t *addr, uint32_t len)
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{
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uint32_t data;
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uint32_t reg;
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uint8_t *buf;
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int ret;
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int i;
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if (len > 8) {
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device_printf(sc->dev, "Failed to read data\n");
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return (-1);
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}
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dprintf("%s: %x\n", __func__, cmd);
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buf = (uint8_t *)addr;
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reg = (cmd << FLASHCMD_CMDOPCODE_S);
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reg |= ((len - 1) << FLASHCMD_NUMRDDATABYTES_S);
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reg |= FLASHCMD_ENRDDATA;
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WRITE4(sc, CQSPI_FLASHCMD, reg);
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reg |= FLASHCMD_EXECCMD;
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WRITE4(sc, CQSPI_FLASHCMD, reg);
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ret = cqspi_wait_for_completion(sc);
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if (ret != 0) {
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device_printf(sc->dev, "%s: cmd failed: %x\n",
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__func__, cmd);
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return (ret);
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}
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data = READ4(sc, CQSPI_FLASHCMDRDDATALO);
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for (i = 0; i < len; i++)
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buf[i] = (data >> (i * 8)) & 0xff;
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return (0);
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}
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static int
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cqspi_wait_ready(struct cqspi_softc *sc)
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{
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uint8_t data;
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do {
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cqspi_cmd_read(sc, CMD_READ_STATUS, &data, 1);
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} while (data & STATUS_WIP);
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return (0);
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}
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static int
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cqspi_write_reg(device_t dev, device_t child,
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uint8_t opcode, uint8_t *addr, uint32_t len)
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{
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struct cqspi_softc *sc;
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int ret;
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sc = device_get_softc(dev);
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ret = cqspi_cmd_write(sc, opcode, addr, len);
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return (ret);
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}
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static int
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cqspi_read_reg(device_t dev, device_t child,
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uint8_t opcode, uint8_t *addr, uint32_t len)
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{
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struct cqspi_softc *sc;
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int ret;
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sc = device_get_softc(dev);
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ret = cqspi_cmd_read(sc, opcode, addr, len);
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return (ret);
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}
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static int
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cqspi_wait_idle(struct cqspi_softc *sc)
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{
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uint32_t reg;
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do {
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reg = READ4(sc, CQSPI_CFG);
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if (reg & CFG_IDLE) {
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break;
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}
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} while (1);
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return (0);
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}
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static int
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cqspi_erase(device_t dev, device_t child, off_t offset)
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{
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struct cqspi_softc *sc;
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sc = device_get_softc(dev);
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cqspi_wait_idle(sc);
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cqspi_wait_ready(sc);
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cqspi_cmd_write(sc, CMD_WRITE_ENABLE, 0, 0);
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cqspi_wait_idle(sc);
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cqspi_wait_ready(sc);
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cqspi_cmd_write_addr(sc, CMD_QUAD_SECTOR_ERASE, offset, 4);
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cqspi_wait_idle(sc);
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return (0);
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}
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static int
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cqspi_write(device_t dev, device_t child, struct bio *bp,
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off_t offset, caddr_t data, off_t count)
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{
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struct cqspi_softc *sc;
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uint32_t reg;
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dprintf("%s: offset 0x%llx count %lld bytes\n",
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__func__, offset, count);
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sc = device_get_softc(dev);
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cqspi_wait_ready(sc);
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cqspi_cmd_write(sc, CMD_WRITE_ENABLE, 0, 0);
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cqspi_wait_idle(sc);
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cqspi_wait_ready(sc);
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cqspi_wait_idle(sc);
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reg = DMAPER_NUMSGLREQBYTES_4;
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reg |= DMAPER_NUMBURSTREQBYTES_4;
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WRITE4(sc, CQSPI_DMAPER, reg);
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WRITE4(sc, CQSPI_INDWRWATER, 64);
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WRITE4(sc, CQSPI_INDWR, INDRD_IND_OPS_DONE_STATUS);
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WRITE4(sc, CQSPI_INDWR, 0);
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WRITE4(sc, CQSPI_INDWRCNT, count);
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WRITE4(sc, CQSPI_INDWRSTADDR, offset);
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reg = (0 << DEVWR_DUMMYWRCLKS_S);
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reg |= DEVWR_DATA_WIDTH_QUAD;
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reg |= DEVWR_ADDR_WIDTH_SINGLE;
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reg |= (CMD_QUAD_PAGE_PROGRAM << DEVWR_WROPCODE_S);
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WRITE4(sc, CQSPI_DEVWR, reg);
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reg = DEVRD_DATA_WIDTH_QUAD;
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reg |= DEVRD_ADDR_WIDTH_SINGLE;
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reg |= DEVRD_INST_WIDTH_SINGLE;
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WRITE4(sc, CQSPI_DEVRD, reg);
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xdma_enqueue_bio(sc->xchan_tx, &bp,
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sc->sram_phys, 4, 4, XDMA_MEM_TO_DEV);
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xdma_queue_submit(sc->xchan_tx);
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sc->write_op_done = 0;
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WRITE4(sc, CQSPI_INDWR, INDRD_START);
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while (sc->write_op_done == 0)
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tsleep(&sc->xdma_tx, PCATCH | PZERO, "spi", hz/2);
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cqspi_wait_idle(sc);
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return (0);
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}
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static int
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cqspi_read(device_t dev, device_t child, struct bio *bp,
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off_t offset, caddr_t data, off_t count)
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{
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struct cqspi_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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dprintf("%s: offset 0x%llx count %lld bytes\n",
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__func__, offset, count);
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cqspi_wait_idle(sc);
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reg = DMAPER_NUMSGLREQBYTES_4;
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reg |= DMAPER_NUMBURSTREQBYTES_4;
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WRITE4(sc, CQSPI_DMAPER, reg);
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WRITE4(sc, CQSPI_INDRDWATER, 64);
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WRITE4(sc, CQSPI_INDRD, INDRD_IND_OPS_DONE_STATUS);
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WRITE4(sc, CQSPI_INDRD, 0);
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WRITE4(sc, CQSPI_INDRDCNT, count);
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WRITE4(sc, CQSPI_INDRDSTADDR, offset);
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reg = (0 << DEVRD_DUMMYRDCLKS_S);
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reg |= DEVRD_DATA_WIDTH_QUAD;
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reg |= DEVRD_ADDR_WIDTH_SINGLE;
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reg |= DEVRD_INST_WIDTH_SINGLE;
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reg |= DEVRD_ENMODEBITS;
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reg |= (CMD_READ_4B_QUAD_OUTPUT << DEVRD_RDOPCODE_S);
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WRITE4(sc, CQSPI_DEVRD, reg);
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WRITE4(sc, CQSPI_MODEBIT, 0xff);
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WRITE4(sc, CQSPI_IRQMASK, 0);
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xdma_enqueue_bio(sc->xchan_rx, &bp, sc->sram_phys, 4, 4,
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XDMA_DEV_TO_MEM);
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xdma_queue_submit(sc->xchan_rx);
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sc->read_op_done = 0;
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WRITE4(sc, CQSPI_INDRD, INDRD_START);
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while (sc->read_op_done == 0)
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tsleep(&sc->xdma_rx, PCATCH | PZERO, "spi", hz/2);
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cqspi_wait_idle(sc);
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|
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return (0);
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}
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|
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static int
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cqspi_init(struct cqspi_softc *sc)
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|
{
|
|
pcell_t dts_value[1];
|
|
phandle_t node;
|
|
uint32_t reg;
|
|
int len;
|
|
|
|
device_printf(sc->dev, "Module ID %x\n",
|
|
READ4(sc, CQSPI_MODULEID));
|
|
|
|
if ((node = ofw_bus_get_node(sc->dev)) == -1) {
|
|
return (ENXIO);
|
|
}
|
|
|
|
if ((len = OF_getproplen(node, "cdns,fifo-depth")) <= 0) {
|
|
return (ENXIO);
|
|
}
|
|
OF_getencprop(node, "cdns,fifo-depth", dts_value, len);
|
|
sc->fifo_depth = dts_value[0];
|
|
|
|
if ((len = OF_getproplen(node, "cdns,fifo-width")) <= 0) {
|
|
return (ENXIO);
|
|
}
|
|
OF_getencprop(node, "cdns,fifo-width", dts_value, len);
|
|
sc->fifo_width = dts_value[0];
|
|
|
|
if ((len = OF_getproplen(node, "cdns,trigger-address")) <= 0) {
|
|
return (ENXIO);
|
|
}
|
|
OF_getencprop(node, "cdns,trigger-address", dts_value, len);
|
|
sc->trigger_address = dts_value[0];
|
|
|
|
/* Disable controller */
|
|
reg = READ4(sc, CQSPI_CFG);
|
|
reg &= ~(CFG_EN);
|
|
WRITE4(sc, CQSPI_CFG, reg);
|
|
|
|
reg = READ4(sc, CQSPI_DEVSZ);
|
|
reg &= ~(DEVSZ_NUMADDRBYTES_M);
|
|
reg |= ((4 - 1) - DEVSZ_NUMADDRBYTES_S);
|
|
WRITE4(sc, CQSPI_DEVSZ, reg);
|
|
|
|
WRITE4(sc, CQSPI_SRAMPART, sc->fifo_depth/2);
|
|
|
|
/* TODO: calculate baud rate and delay values. */
|
|
|
|
reg = READ4(sc, CQSPI_CFG);
|
|
/* Configure baud rate */
|
|
reg &= ~(CFG_BAUD_M);
|
|
reg |= CFG_BAUD12;
|
|
reg |= CFG_ENDMA;
|
|
WRITE4(sc, CQSPI_CFG, reg);
|
|
|
|
reg = (3 << DELAY_NSS_S);
|
|
reg |= (3 << DELAY_BTWN_S);
|
|
reg |= (1 << DELAY_AFTER_S);
|
|
reg |= (1 << DELAY_INIT_S);
|
|
WRITE4(sc, CQSPI_DELAY, reg);
|
|
|
|
READ4(sc, CQSPI_RDDATACAP);
|
|
reg &= ~(RDDATACAP_DELAY_M);
|
|
reg |= (1 << RDDATACAP_DELAY_S);
|
|
WRITE4(sc, CQSPI_RDDATACAP, reg);
|
|
|
|
/* Enable controller */
|
|
reg = READ4(sc, CQSPI_CFG);
|
|
reg |= (CFG_EN);
|
|
WRITE4(sc, CQSPI_CFG, reg);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cqspi_add_devices(device_t dev)
|
|
{
|
|
phandle_t child, node;
|
|
device_t child_dev;
|
|
int error;
|
|
|
|
node = ofw_bus_get_node(dev);
|
|
|
|
for (child = OF_child(node); child != 0; child = OF_peer(child)) {
|
|
child_dev =
|
|
simplebus_add_device(dev, child, 0, NULL, -1, NULL);
|
|
if (child_dev == NULL) {
|
|
return (ENXIO);
|
|
}
|
|
|
|
error = device_probe_and_attach(child_dev);
|
|
if (error != 0) {
|
|
printf("can't probe and attach: %d\n", error);
|
|
}
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
cqspi_delayed_attach(void *arg)
|
|
{
|
|
struct cqspi_softc *sc;
|
|
|
|
sc = arg;
|
|
|
|
cqspi_add_devices(sc->dev);
|
|
bus_generic_attach(sc->dev);
|
|
|
|
config_intrhook_disestablish(&sc->config_intrhook);
|
|
}
|
|
|
|
static int
|
|
cqspi_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev)) {
|
|
return (ENXIO);
|
|
}
|
|
|
|
if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
|
|
return (ENXIO);
|
|
}
|
|
|
|
device_set_desc(dev, "Cadence Quad SPI controller");
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cqspi_attach(device_t dev)
|
|
{
|
|
struct cqspi_softc *sc;
|
|
uint32_t caps;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
|
|
if (bus_alloc_resources(dev, cqspi_spec, sc->res)) {
|
|
device_printf(dev, "could not allocate resources\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Memory interface */
|
|
sc->bst = rman_get_bustag(sc->res[0]);
|
|
sc->bsh = rman_get_bushandle(sc->res[0]);
|
|
|
|
sc->sram_phys = rman_get_start(sc->res[1]);
|
|
|
|
/* Setup interrupt handlers */
|
|
if (bus_setup_intr(sc->dev, sc->res[2], INTR_TYPE_BIO | INTR_MPSAFE,
|
|
NULL, cqspi_intr, sc, &sc->ih)) {
|
|
device_printf(sc->dev, "Unable to setup intr\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
CQSPI_LOCK_INIT(sc);
|
|
|
|
caps = 0;
|
|
|
|
/* Get xDMA controller. */
|
|
sc->xdma_tx = xdma_ofw_get(sc->dev, "tx");
|
|
if (sc->xdma_tx == NULL) {
|
|
device_printf(dev, "Can't find DMA controller.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->xdma_rx = xdma_ofw_get(sc->dev, "rx");
|
|
if (sc->xdma_rx == NULL) {
|
|
device_printf(dev, "Can't find DMA controller.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Alloc xDMA virtual channels. */
|
|
sc->xchan_tx = xdma_channel_alloc(sc->xdma_tx, caps);
|
|
if (sc->xchan_tx == NULL) {
|
|
device_printf(dev, "Can't alloc virtual DMA channel.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->xchan_rx = xdma_channel_alloc(sc->xdma_rx, caps);
|
|
if (sc->xchan_rx == NULL) {
|
|
device_printf(dev, "Can't alloc virtual DMA channel.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Setup xDMA interrupt handlers. */
|
|
error = xdma_setup_intr(sc->xchan_tx, 0, cqspi_xdma_tx_intr,
|
|
sc, &sc->ih_tx);
|
|
if (error) {
|
|
device_printf(sc->dev,
|
|
"Can't setup xDMA interrupt handler.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
error = xdma_setup_intr(sc->xchan_rx, 0, cqspi_xdma_rx_intr,
|
|
sc, &sc->ih_rx);
|
|
if (error) {
|
|
device_printf(sc->dev,
|
|
"Can't setup xDMA interrupt handler.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
xdma_prep_sg(sc->xchan_tx, TX_QUEUE_SIZE, maxphys, 8, 16, 0,
|
|
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR);
|
|
xdma_prep_sg(sc->xchan_rx, TX_QUEUE_SIZE, maxphys, 8, 16, 0,
|
|
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR);
|
|
|
|
cqspi_init(sc);
|
|
|
|
sc->config_intrhook.ich_func = cqspi_delayed_attach;
|
|
sc->config_intrhook.ich_arg = sc;
|
|
if (config_intrhook_establish(&sc->config_intrhook) != 0) {
|
|
device_printf(dev, "config_intrhook_establish failed\n");
|
|
return (ENOMEM);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cqspi_detach(device_t dev)
|
|
{
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static device_method_t cqspi_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, cqspi_probe),
|
|
DEVMETHOD(device_attach, cqspi_attach),
|
|
DEVMETHOD(device_detach, cqspi_detach),
|
|
|
|
/* Quad SPI Flash Interface */
|
|
DEVMETHOD(qspi_read_reg, cqspi_read_reg),
|
|
DEVMETHOD(qspi_write_reg, cqspi_write_reg),
|
|
DEVMETHOD(qspi_read, cqspi_read),
|
|
DEVMETHOD(qspi_write, cqspi_write),
|
|
DEVMETHOD(qspi_erase, cqspi_erase),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
DEFINE_CLASS_1(cqspi, cqspi_driver, cqspi_methods,
|
|
sizeof(struct cqspi_softc), simplebus_driver);
|
|
|
|
DRIVER_MODULE(cqspi, simplebus, cqspi_driver, 0, 0);
|