338 lines
7.7 KiB
C
338 lines
7.7 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2017 Tom Jones <tj@enoti.me>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2016 Mark Kettenis
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#define CHVGPIO_INTERRUPT_STATUS 0x0300
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#define CHVGPIO_INTERRUPT_MASK 0x0380
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#define CHVGPIO_PAD_CFG0 0x4400
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#define CHVGPIO_PAD_CFG1 0x4404
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#define CHVGPIO_PAD_CFG0_GPIORXSTATE 0x00000001
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#define CHVGPIO_PAD_CFG0_GPIOTXSTATE 0x00000002
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#define CHVGPIO_PAD_CFG0_INTSEL_MASK 0xf0000000
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#define CHVGPIO_PAD_CFG0_INTSEL_SHIFT 28
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#define CHVGPIO_PAD_CFG0_GPIOCFG_SHIFT 8
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#define CHVGPIO_PAD_CFG0_GPIOCFG_MASK (7 << CHVGPIO_PAD_CFG0_GPIOCFG_SHIFT)
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#define CHVGPIO_PAD_CFG0_GPIOCFG_GPIO 0
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#define CHVGPIO_PAD_CFG0_GPIOCFG_GPO 1
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#define CHVGPIO_PAD_CFG0_GPIOCFG_GPI 2
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#define CHVGPIO_PAD_CFG0_GPIOCFG_HIZ 3
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#define CHVGPIO_PAD_CFG1_INTWAKECFG_MASK 0x00000007
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#define CHVGPIO_PAD_CFG1_INTWAKECFG_FALLING 0x00000001
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#define CHVGPIO_PAD_CFG1_INTWAKECFG_RISING 0x00000002
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#define CHVGPIO_PAD_CFG1_INTWAKECFG_BOTH 0x00000003
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#define CHVGPIO_PAD_CFG1_INTWAKECFG_LEVEL 0x00000004
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#define CHVGPIO_PAD_CFG1_INVRXTX_MASK 0x000000f0
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#define CHVGPIO_PAD_CFG1_INVRXTX_RXDATA 0x00000040
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/*
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* The pads for the pins are arranged in groups of maximal 15 pins.
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* The arrays below give the number of pins per group, such that we
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* can validate the (untrusted) pin numbers from ACPI.
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*/
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#define E_UID 3
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#define E_BANK_PREFIX "eastbank"
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const int chv_east_pins[] = {
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12, 12, -1
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};
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const char *chv_east_pin_names[] = {
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"PMU_SLP_S3_B",
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"PMU_BATLOW_B",
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"SUS_STAT_B",
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"PMU_SLP_S0IX_B",
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"PMU_AC_PRESENT",
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"PMU_PLTRST_B",
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"PMU_SUSCLK",
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"PMU_SLP_LAN_B",
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"PMU_PWRBTN_B",
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"PMU_SLP_S4_B",
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"PMU_WAKE_B",
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"PMU_WAKE_LAN_B"
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"MF_ISH_GPIO_3",
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"MF_ISH_GPIO_7",
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"MF_ISH_I2C1_SCL",
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"MF_ISH_GPIO_1",
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"MF_ISH_GPIO_5",
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"MF_ISH_GPIO_9",
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"MF_ISH_GPIO_0",
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"MF_ISH_GPIO_4",
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"MF_ISH_GPIO_8",
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"MF_ISH_GPIO_2",
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"MF_ISH_GPIO_6",
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"MF_ISH_I2C1_SDA"
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};
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#define N_UID 2
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#define N_BANK_PREFIX "northbank"
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const int chv_north_pins[] = {
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9, 13, 12, 12, 13, -1
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};
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const char *chv_north_pin_names[] = {
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"GPIO_DFX0_PAD",
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"GPIO_DFX3_PAD",
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"GPIO_DFX7_PAD",
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"GPIO_DFX1_PAD",
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"GPIO_DFX5_PAD",
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"GPIO_DFX4_PAD",
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"GPIO_DFX8_PAD",
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"GPIO_DFX2_PAD",
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"GPIO_DFX6_PAD",
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"GPIO_SUS0_PAD",
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"SEC_GPIO_SUS10_PAD",
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"GPIO_SUS3_PAD",
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"GPIO_SUS7_PAD",
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"GPIO_SUS1_PAD",
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"GPIO_SUS5_PAD",
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"SEC_GPIO_SUS11_PAD",
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"GPIO_SUS4_PAD",
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"SEC_GPIO_SUS8_PAD",
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"GPIO_SUS2_PAD",
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"GPIO_SUS6_PAD",
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"CX_PREQ_B_PAD",
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"SEC_GPIO_SUS9_PAD",
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"TRST_B_PAD",
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"TCK_PAD",
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"PROCHOT_B_PAD",
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"SVID0_DATA_PAD",
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"TMS_PAD",
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"CX_PRDY_B_2_PAD",
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"TDO_2_PAD",
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"CX_PRDY_B_PAD",
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"SVID0_ALERT_B_PAD",
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"TDO_PAD",
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"SVID0_CLK_PAD",
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"TDI_PAD",
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"GP_CAMERASB05_PAD",
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"GP_CAMERASB02_PAD",
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"GP_CAMERASB08_PAD",
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"GP_CAMERASB00_PAD",
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"GP_CAMERASB06_PAD",
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"GP_CAMERASB10_PAD",
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"GP_CAMERASB03_PAD",
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"GP_CAMERASB09_PAD",
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"GP_CAMERASB01_PAD",
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"GP_CAMERASB07_PAD",
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"GP_CAMERASB11_PAD",
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"GP_CAMERASB04_PAD",
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"PANEL0_BKLTEN_PAD",
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"HV_DDI0_HPD_PAD",
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"HV_DDI2_DDC_SDA_PAD",
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"PANEL1_BKLTCTL_PAD",
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"HV_DDI1_HPD_PAD",
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"PANEL0_BKLTCTL_PAD",
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"HV_DDI0_DDC_SDA_PAD",
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"HV_DDI2_DDC_SCL_PAD",
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"HV_DDI2_HPD_PAD",
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"PANEL1_VDDEN_PAD",
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"PANEL1_BKLTEN_PAD",
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"HV_DDI0_DDC_SCL_PAD",
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"PANEL0_VDDEN_PAD",
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};
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#define SE_UID 4
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#define SE_BANK_PREFIX "southeastbank"
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const int chv_southeast_pins[] = {
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8, 12, 6, 8, 10, 11, -1
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};
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const char *chv_southeast_pin_names[] = {
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"MF_PLT_CLK0_PAD",
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"PWM1_PAD",
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"MF_PLT_CLK1_PAD",
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"MF_PLT_CLK4_PAD",
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"MF_PLT_CLK3_PAD",
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"PWM0_PAD",
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"MF_PLT_CLK5_PAD",
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"MF_PLT_CLK2_PAD",
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"SDMMC2_D3_CD_B_PAD",
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"SDMMC1_CLK_PAD",
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"SDMMC1_D0_PAD",
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"SDMMC2_D1_PAD",
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"SDMMC2_CLK_PAD",
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"SDMMC1_D2_PAD",
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"SDMMC2_D2_PAD",
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"SDMMC2_CMD_PAD",
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"SDMMC1_CMD_PAD",
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"SDMMC1_D1_PAD",
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"SDMMC2_D0_PAD",
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"SDMMC1_D3_CD_B_PAD",
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"SDMMC3_D1_PAD",
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"SDMMC3_CLK_PAD",
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"SDMMC3_D3_PAD",
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"SDMMC3_D2_PAD",
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"SDMMC3_CMD_PAD",
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"SDMMC3_D0_PAD",
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"MF_LPC_AD2_PAD",
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"LPC_CLKRUNB_PAD",
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"MF_LPC_AD0_PAD",
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"LPC_FRAMEB_PAD",
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"MF_LPC_CLKOUT1_PAD",
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"MF_LPC_AD3_PAD",
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"MF_LPC_CLKOUT0_PAD",
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"MF_LPC_AD1_PAD",
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"SPI1_MISO_PAD",
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"SPI1_CS0_B_PAD",
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"SPI1_CLK_PAD",
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"MMC1_D6_PAD",
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"SPI1_MOSI_PAD",
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"MMC1_D5_PAD",
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"SPI1_CS1_B_PAD",
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"MMC1_D4_SD_WE_PAD",
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"MMC1_D7_PAD",
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"MMC1_RCLK_PAD",
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"USB_OC1_B_PAD",
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"PMU_RESETBUTTON_B_PAD",
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"GPIO_ALERT_PAD",
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"SDMMC3_PWR_EN_B_PAD",
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"ILB_SERIRQ_PAD",
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"USB_OC0_B_PAD",
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"SDMMC3_CD_B_PAD",
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"SPKR_PAD",
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"SUSPWRDNACK_PAD",
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"SPARE_PIN_PAD",
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"SDMMC3_1P8_EN_PAD",
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};
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#define SW_UID 1
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#define SW_BANK_PREFIX "southwestbank"
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const int chv_southwest_pins[] = {
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8, 8, 8, 8, 8, 8, 8, -1
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};
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const char *chv_southwest_pin_names[] = {
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"FST_SPI_D2_PAD",
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"FST_SPI_D0_PAD",
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"FST_SPI_CLK_PAD",
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"FST_SPI_D3_PAD",
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"FST_SPI_CS1_B_PAD",
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"FST_SPI_D1_PAD",
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"FST_SPI_CS0_B_PAD",
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"FST_SPI_CS2_B_PAD",
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"UART1_RTS_B_PAD",
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"UART1_RXD_PAD",
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"UART2_RXD_PAD",
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"UART1_CTS_B_PAD",
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"UART2_RTS_B_PAD",
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"UART1_TXD_PAD",
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"UART2_TXD_PAD",
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"UART2_CTS_B_PAD",
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"MF_HDA_CLK"
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"MF_HDA_RSTB",
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"MF_HDA_SDIO",
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"MF_HDA_SDO",
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"MF_HDA_DOCKRSTB",
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"MF_HDA_SYNC",
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"MF_HDA_SDI1",
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"MF_HDA_DOCKENB",
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"I2C5_SDA_PAD",
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"I2C4_SDA_PAD",
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"I2C6_SDA_PAD",
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"I2C5_SCL_PAD",
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"I2C_NFC_SDA_PAD",
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"I2C4_SCL_PAD",
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"I2C6_SCL_PAD",
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"I2C_NFC_SCL_PAD",
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"I2C1_SDA_PAD",
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"I2C0_SDA_PAD",
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"I2C2_SDA_PAD",
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"I2C1_SCL_PAD",
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"I2C3_SDA_PAD",
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"I2C0_SCL_PAD",
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"I2C2_SCL_PAD",
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"I2C3_SCL_PAD",
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"SATA_GP0",
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"SATA_GP1",
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"SATA_LEDN",
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"SATA_GP2",
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"MF_SMB_ALERTB",
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"SATA_GP3",
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"MF_SMB_CLK",
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"MF_SMB_DATA",
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"PCIE_CLKREQ0B_PAD",
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"PCIE_CLKREQ1B_PAD",
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"GP_SSP_2_CLK_PAD",
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"PCIE_CLKREQ2B_PAD",
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"GP_SSP_2_RXD_PAD",
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"PCIE_CLKREQ3B_PAD",
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"GP_SSP_2_FS_PAD",
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"GP_SSP_2_TXD_PAD",
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};
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const char *virtualgpio[] = {
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"VIRTUAL0_PAD",
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"VIRTUAL1_PAD",
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"VIRTUAL2_PAD",
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"VIRTUAL3_PAD",
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"VIRTUAL4_PAD",
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"VIRTUAL5_PAD",
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"VIRTUAL6_PAD",
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"VIRTUAL7_PAD",
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};
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