Reviewed by: markj MFC after: 3 days Differential Revision: https://reviews.freebsd.org/D41281
806 lines
21 KiB
C
806 lines
21 KiB
C
/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2023 Google LLC
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "gve.h"
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#include "gve_adminq.h"
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#define GVE_GQ_TX_MIN_PKT_DESC_BYTES 182
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static int
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gve_tx_fifo_init(struct gve_priv *priv, struct gve_tx_ring *tx)
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{
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struct gve_queue_page_list *qpl = tx->com.qpl;
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struct gve_tx_fifo *fifo = &tx->fifo;
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fifo->size = qpl->num_pages * PAGE_SIZE;
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fifo->base = qpl->kva;
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atomic_store_int(&fifo->available, fifo->size);
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fifo->head = 0;
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return (0);
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}
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static void
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gve_tx_free_ring(struct gve_priv *priv, int i)
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{
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struct gve_tx_ring *tx = &priv->tx[i];
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struct gve_ring_com *com = &tx->com;
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/* Safe to call even if never alloced */
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gve_free_counters((counter_u64_t *)&tx->stats, NUM_TX_STATS);
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if (tx->br != NULL) {
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buf_ring_free(tx->br, M_DEVBUF);
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tx->br = NULL;
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}
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if (mtx_initialized(&tx->ring_mtx))
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mtx_destroy(&tx->ring_mtx);
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if (tx->info != NULL) {
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free(tx->info, M_GVE);
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tx->info = NULL;
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}
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if (tx->desc_ring != NULL) {
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gve_dma_free_coherent(&tx->desc_ring_mem);
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tx->desc_ring = NULL;
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}
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if (com->q_resources != NULL) {
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gve_dma_free_coherent(&com->q_resources_mem);
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com->q_resources = NULL;
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}
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}
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static int
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gve_tx_alloc_ring(struct gve_priv *priv, int i)
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{
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struct gve_tx_ring *tx = &priv->tx[i];
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struct gve_ring_com *com = &tx->com;
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char mtx_name[16];
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int err;
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com->priv = priv;
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com->id = i;
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com->qpl = &priv->qpls[i];
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if (com->qpl == NULL) {
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device_printf(priv->dev, "No QPL left for tx ring %d\n", i);
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return (ENOMEM);
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}
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err = gve_tx_fifo_init(priv, tx);
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if (err != 0)
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goto abort;
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tx->info = malloc(sizeof(struct gve_tx_buffer_state) * priv->tx_desc_cnt,
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M_GVE, M_WAITOK | M_ZERO);
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sprintf(mtx_name, "gvetx%d", i);
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mtx_init(&tx->ring_mtx, mtx_name, NULL, MTX_DEF);
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tx->br = buf_ring_alloc(GVE_TX_BUFRING_ENTRIES, M_DEVBUF,
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M_WAITOK, &tx->ring_mtx);
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gve_alloc_counters((counter_u64_t *)&tx->stats, NUM_TX_STATS);
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err = gve_dma_alloc_coherent(priv, sizeof(struct gve_queue_resources),
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PAGE_SIZE, &com->q_resources_mem);
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if (err != 0) {
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device_printf(priv->dev, "Failed to alloc queue resources for tx ring %d", i);
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goto abort;
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}
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com->q_resources = com->q_resources_mem.cpu_addr;
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err = gve_dma_alloc_coherent(priv,
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sizeof(union gve_tx_desc) * priv->tx_desc_cnt,
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CACHE_LINE_SIZE, &tx->desc_ring_mem);
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if (err != 0) {
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device_printf(priv->dev, "Failed to alloc desc ring for tx ring %d", i);
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goto abort;
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}
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tx->desc_ring = tx->desc_ring_mem.cpu_addr;
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return (0);
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abort:
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gve_tx_free_ring(priv, i);
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return (err);
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}
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int
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gve_alloc_tx_rings(struct gve_priv *priv)
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{
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int err = 0;
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int i;
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priv->tx = malloc(sizeof(struct gve_tx_ring) * priv->tx_cfg.num_queues,
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M_GVE, M_WAITOK | M_ZERO);
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for (i = 0; i < priv->tx_cfg.num_queues; i++) {
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err = gve_tx_alloc_ring(priv, i);
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if (err != 0)
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goto free_rings;
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}
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return (0);
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free_rings:
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while (i--)
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gve_tx_free_ring(priv, i);
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free(priv->tx, M_GVE);
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return (err);
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}
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void
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gve_free_tx_rings(struct gve_priv *priv)
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{
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int i;
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for (i = 0; i < priv->tx_cfg.num_queues; i++)
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gve_tx_free_ring(priv, i);
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free(priv->tx, M_GVE);
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}
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static void
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gve_tx_clear_desc_ring(struct gve_tx_ring *tx)
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{
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struct gve_ring_com *com = &tx->com;
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int i;
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for (i = 0; i < com->priv->tx_desc_cnt; i++) {
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tx->desc_ring[i] = (union gve_tx_desc){};
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tx->info[i] = (struct gve_tx_buffer_state){};
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}
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bus_dmamap_sync(tx->desc_ring_mem.tag, tx->desc_ring_mem.map,
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BUS_DMASYNC_PREWRITE);
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}
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static void
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gve_clear_tx_ring(struct gve_priv *priv, int i)
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{
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struct gve_tx_ring *tx = &priv->tx[i];
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struct gve_tx_fifo *fifo = &tx->fifo;
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tx->req = 0;
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tx->done = 0;
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tx->mask = priv->tx_desc_cnt - 1;
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atomic_store_int(&fifo->available, fifo->size);
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fifo->head = 0;
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gve_tx_clear_desc_ring(tx);
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}
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static void
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gve_start_tx_ring(struct gve_priv *priv, int i)
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{
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struct gve_tx_ring *tx = &priv->tx[i];
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struct gve_ring_com *com = &tx->com;
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NET_TASK_INIT(&com->cleanup_task, 0, gve_tx_cleanup_tq, tx);
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com->cleanup_tq = taskqueue_create_fast("gve tx", M_WAITOK,
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taskqueue_thread_enqueue, &com->cleanup_tq);
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taskqueue_start_threads(&com->cleanup_tq, 1, PI_NET, "%s txq %d",
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device_get_nameunit(priv->dev), i);
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TASK_INIT(&tx->xmit_task, 0, gve_xmit_tq, tx);
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tx->xmit_tq = taskqueue_create_fast("gve tx xmit",
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M_WAITOK, taskqueue_thread_enqueue, &tx->xmit_tq);
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taskqueue_start_threads(&tx->xmit_tq, 1, PI_NET, "%s txq %d xmit",
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device_get_nameunit(priv->dev), i);
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}
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int
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gve_create_tx_rings(struct gve_priv *priv)
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{
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struct gve_ring_com *com;
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struct gve_tx_ring *tx;
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int err;
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int i;
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if (gve_get_state_flag(priv, GVE_STATE_FLAG_TX_RINGS_OK))
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return (0);
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for (i = 0; i < priv->tx_cfg.num_queues; i++)
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gve_clear_tx_ring(priv, i);
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err = gve_adminq_create_tx_queues(priv, priv->tx_cfg.num_queues);
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if (err != 0)
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return (err);
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bus_dmamap_sync(priv->irqs_db_mem.tag, priv->irqs_db_mem.map,
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BUS_DMASYNC_POSTREAD);
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for (i = 0; i < priv->tx_cfg.num_queues; i++) {
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tx = &priv->tx[i];
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com = &tx->com;
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com->irq_db_offset = 4 * be32toh(priv->irq_db_indices[com->ntfy_id].index);
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bus_dmamap_sync(com->q_resources_mem.tag, com->q_resources_mem.map,
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BUS_DMASYNC_POSTREAD);
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com->db_offset = 4 * be32toh(com->q_resources->db_index);
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com->counter_idx = be32toh(com->q_resources->counter_index);
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gve_start_tx_ring(priv, i);
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}
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gve_set_state_flag(priv, GVE_STATE_FLAG_TX_RINGS_OK);
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return (0);
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}
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static void
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gve_stop_tx_ring(struct gve_priv *priv, int i)
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{
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struct gve_tx_ring *tx = &priv->tx[i];
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struct gve_ring_com *com = &tx->com;
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if (com->cleanup_tq != NULL) {
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taskqueue_quiesce(com->cleanup_tq);
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taskqueue_free(com->cleanup_tq);
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com->cleanup_tq = NULL;
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}
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if (tx->xmit_tq != NULL) {
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taskqueue_quiesce(tx->xmit_tq);
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taskqueue_free(tx->xmit_tq);
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tx->xmit_tq = NULL;
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}
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}
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int
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gve_destroy_tx_rings(struct gve_priv *priv)
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{
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int err;
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int i;
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for (i = 0; i < priv->tx_cfg.num_queues; i++)
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gve_stop_tx_ring(priv, i);
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if (gve_get_state_flag(priv, GVE_STATE_FLAG_TX_RINGS_OK)) {
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err = gve_adminq_destroy_tx_queues(priv, priv->tx_cfg.num_queues);
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if (err != 0)
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return (err);
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gve_clear_state_flag(priv, GVE_STATE_FLAG_TX_RINGS_OK);
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}
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return (0);
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}
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int
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gve_tx_intr(void *arg)
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{
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struct gve_tx_ring *tx = arg;
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struct gve_priv *priv = tx->com.priv;
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struct gve_ring_com *com = &tx->com;
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if (__predict_false((if_getdrvflags(priv->ifp) & IFF_DRV_RUNNING) == 0))
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return (FILTER_STRAY);
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gve_db_bar_write_4(priv, com->irq_db_offset, GVE_IRQ_MASK);
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taskqueue_enqueue(com->cleanup_tq, &com->cleanup_task);
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return (FILTER_HANDLED);
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}
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static uint32_t
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gve_tx_load_event_counter(struct gve_priv *priv, struct gve_tx_ring *tx)
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{
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bus_dmamap_sync(priv->counter_array_mem.tag, priv->counter_array_mem.map,
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BUS_DMASYNC_POSTREAD);
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uint32_t counter = priv->counters[tx->com.counter_idx];
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return (be32toh(counter));
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}
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static void
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gve_tx_free_fifo(struct gve_tx_fifo *fifo, size_t bytes)
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{
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atomic_add_int(&fifo->available, bytes);
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}
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void
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gve_tx_cleanup_tq(void *arg, int pending)
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{
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struct gve_tx_ring *tx = arg;
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struct gve_priv *priv = tx->com.priv;
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uint32_t nic_done = gve_tx_load_event_counter(priv, tx);
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uint32_t todo = nic_done - tx->done;
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size_t space_freed = 0;
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int i, j;
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if (__predict_false((if_getdrvflags(priv->ifp) & IFF_DRV_RUNNING) == 0))
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return;
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for (j = 0; j < todo; j++) {
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uint32_t idx = tx->done & tx->mask;
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struct gve_tx_buffer_state *info = &tx->info[idx];
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struct mbuf *mbuf = info->mbuf;
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tx->done++;
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if (mbuf == NULL)
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continue;
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info->mbuf = NULL;
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counter_enter();
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counter_u64_add_protected(tx->stats.tbytes, mbuf->m_pkthdr.len);
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counter_u64_add_protected(tx->stats.tpackets, 1);
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counter_exit();
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m_freem(mbuf);
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for (i = 0; i < GVE_TX_MAX_DESCS; i++) {
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space_freed += info->iov[i].iov_len + info->iov[i].iov_padding;
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info->iov[i].iov_len = 0;
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info->iov[i].iov_padding = 0;
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}
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}
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gve_tx_free_fifo(&tx->fifo, space_freed);
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gve_db_bar_write_4(priv, tx->com.irq_db_offset,
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GVE_IRQ_ACK | GVE_IRQ_EVENT);
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/*
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* Completions born before this barrier MAY NOT cause the NIC to send an
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* interrupt but they will still be handled by the enqueue below.
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* Completions born after the barrier WILL trigger an interrupt.
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*/
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mb();
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nic_done = gve_tx_load_event_counter(priv, tx);
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todo = nic_done - tx->done;
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if (todo != 0) {
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gve_db_bar_write_4(priv, tx->com.irq_db_offset, GVE_IRQ_MASK);
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taskqueue_enqueue(tx->com.cleanup_tq, &tx->com.cleanup_task);
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}
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}
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static void
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gve_dma_sync_for_device(struct gve_queue_page_list *qpl,
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uint64_t iov_offset, uint64_t iov_len)
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{
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uint64_t last_page = (iov_offset + iov_len - 1) / PAGE_SIZE;
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uint64_t first_page = iov_offset / PAGE_SIZE;
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struct gve_dma_handle *dma;
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uint64_t page;
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for (page = first_page; page <= last_page; page++) {
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dma = &(qpl->dmas[page]);
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bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
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}
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}
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static void
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gve_tx_fill_mtd_desc(struct gve_tx_mtd_desc *mtd_desc, struct mbuf *mbuf)
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{
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mtd_desc->type_flags = GVE_TXD_MTD | GVE_MTD_SUBTYPE_PATH;
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mtd_desc->path_state = GVE_MTD_PATH_STATE_DEFAULT | GVE_MTD_PATH_HASH_L4;
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mtd_desc->path_hash = htobe32(mbuf->m_pkthdr.flowid);
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mtd_desc->reserved0 = 0;
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mtd_desc->reserved1 = 0;
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}
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static void
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gve_tx_fill_pkt_desc(struct gve_tx_pkt_desc *pkt_desc, bool is_tso,
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uint16_t l4_hdr_offset, uint32_t desc_cnt,
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uint16_t first_seg_len, uint64_t addr, bool has_csum_flag,
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int csum_offset, uint16_t pkt_len)
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{
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if (is_tso) {
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pkt_desc->type_flags = GVE_TXD_TSO | GVE_TXF_L4CSUM;
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pkt_desc->l4_csum_offset = csum_offset >> 1;
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pkt_desc->l4_hdr_offset = l4_hdr_offset >> 1;
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} else if (has_csum_flag) {
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pkt_desc->type_flags = GVE_TXD_STD | GVE_TXF_L4CSUM;
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pkt_desc->l4_csum_offset = csum_offset >> 1;
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pkt_desc->l4_hdr_offset = l4_hdr_offset >> 1;
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} else {
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pkt_desc->type_flags = GVE_TXD_STD;
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pkt_desc->l4_csum_offset = 0;
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pkt_desc->l4_hdr_offset = 0;
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}
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pkt_desc->desc_cnt = desc_cnt;
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pkt_desc->len = htobe16(pkt_len);
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pkt_desc->seg_len = htobe16(first_seg_len);
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pkt_desc->seg_addr = htobe64(addr);
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}
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static void
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gve_tx_fill_seg_desc(struct gve_tx_seg_desc *seg_desc,
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bool is_tso, uint16_t len, uint64_t addr,
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bool is_ipv6, uint8_t l3_off, uint16_t tso_mss)
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{
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seg_desc->type_flags = GVE_TXD_SEG;
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if (is_tso) {
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if (is_ipv6)
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seg_desc->type_flags |= GVE_TXSF_IPV6;
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seg_desc->l3_offset = l3_off >> 1;
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seg_desc->mss = htobe16(tso_mss);
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}
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seg_desc->seg_len = htobe16(len);
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seg_desc->seg_addr = htobe64(addr);
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}
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static inline uint32_t
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gve_tx_avail(struct gve_tx_ring *tx)
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{
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return (tx->mask + 1 - (tx->req - tx->done));
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}
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static bool
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gve_tx_fifo_can_alloc(struct gve_tx_fifo *fifo, size_t bytes)
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{
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return (atomic_load_int(&fifo->available) >= bytes);
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}
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static inline bool
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gve_can_tx(struct gve_tx_ring *tx, int bytes_required)
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{
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return (gve_tx_avail(tx) >= (GVE_TX_MAX_DESCS + 1) &&
|
|
gve_tx_fifo_can_alloc(&tx->fifo, bytes_required));
|
|
}
|
|
|
|
static int
|
|
gve_tx_fifo_pad_alloc_one_frag(struct gve_tx_fifo *fifo, size_t bytes)
|
|
{
|
|
return (fifo->head + bytes < fifo->size) ? 0 : fifo->size - fifo->head;
|
|
}
|
|
|
|
static inline int
|
|
gve_fifo_bytes_required(struct gve_tx_ring *tx, uint16_t first_seg_len,
|
|
uint16_t pkt_len)
|
|
{
|
|
int pad_bytes, align_hdr_pad;
|
|
int bytes;
|
|
|
|
pad_bytes = gve_tx_fifo_pad_alloc_one_frag(&tx->fifo, first_seg_len);
|
|
/* We need to take into account the header alignment padding. */
|
|
align_hdr_pad = roundup2(first_seg_len, CACHE_LINE_SIZE) - first_seg_len;
|
|
bytes = align_hdr_pad + pad_bytes + pkt_len;
|
|
|
|
return (bytes);
|
|
}
|
|
|
|
static int
|
|
gve_tx_alloc_fifo(struct gve_tx_fifo *fifo, size_t bytes,
|
|
struct gve_tx_iovec iov[2])
|
|
{
|
|
size_t overflow, padding;
|
|
uint32_t aligned_head;
|
|
int nfrags = 0;
|
|
|
|
if (bytes == 0)
|
|
return (0);
|
|
|
|
/*
|
|
* This check happens before we know how much padding is needed to
|
|
* align to a cacheline boundary for the payload, but that is fine,
|
|
* because the FIFO head always start aligned, and the FIFO's boundaries
|
|
* are aligned, so if there is space for the data, there is space for
|
|
* the padding to the next alignment.
|
|
*/
|
|
KASSERT(gve_tx_fifo_can_alloc(fifo, bytes),
|
|
("Allocating gve tx fifo when there is no room"));
|
|
|
|
nfrags++;
|
|
|
|
iov[0].iov_offset = fifo->head;
|
|
iov[0].iov_len = bytes;
|
|
fifo->head += bytes;
|
|
|
|
if (fifo->head > fifo->size) {
|
|
/*
|
|
* If the allocation did not fit in the tail fragment of the
|
|
* FIFO, also use the head fragment.
|
|
*/
|
|
nfrags++;
|
|
overflow = fifo->head - fifo->size;
|
|
iov[0].iov_len -= overflow;
|
|
iov[1].iov_offset = 0; /* Start of fifo*/
|
|
iov[1].iov_len = overflow;
|
|
|
|
fifo->head = overflow;
|
|
}
|
|
|
|
/* Re-align to a cacheline boundary */
|
|
aligned_head = roundup2(fifo->head, CACHE_LINE_SIZE);
|
|
padding = aligned_head - fifo->head;
|
|
iov[nfrags - 1].iov_padding = padding;
|
|
atomic_add_int(&fifo->available, -(bytes + padding));
|
|
fifo->head = aligned_head;
|
|
|
|
if (fifo->head == fifo->size)
|
|
fifo->head = 0;
|
|
|
|
return (nfrags);
|
|
}
|
|
|
|
/* Only error this returns is ENOBUFS when the tx fifo is short of space */
|
|
static int
|
|
gve_xmit(struct gve_tx_ring *tx, struct mbuf *mbuf)
|
|
{
|
|
bool is_tso, has_csum_flag, is_ipv6 = false, is_tcp = false, is_udp = false;
|
|
int csum_flags, csum_offset, mtd_desc_nr, offset, copy_offset;
|
|
uint16_t tso_mss, l4_off, l4_data_off, pkt_len, first_seg_len;
|
|
int pad_bytes, hdr_nfrags, payload_nfrags;
|
|
struct gve_tx_pkt_desc *pkt_desc;
|
|
struct gve_tx_seg_desc *seg_desc;
|
|
struct gve_tx_mtd_desc *mtd_desc;
|
|
struct gve_tx_buffer_state *info;
|
|
uint32_t idx = tx->req & tx->mask;
|
|
struct ether_header *eh;
|
|
struct mbuf *mbuf_next;
|
|
int payload_iov = 2;
|
|
int bytes_required;
|
|
struct ip6_hdr *ip6;
|
|
struct tcphdr *th;
|
|
uint32_t next_idx;
|
|
uint8_t l3_off;
|
|
struct ip *ip;
|
|
int i;
|
|
|
|
info = &tx->info[idx];
|
|
csum_flags = mbuf->m_pkthdr.csum_flags;
|
|
pkt_len = mbuf->m_pkthdr.len;
|
|
is_tso = csum_flags & CSUM_TSO;
|
|
has_csum_flag = csum_flags & (CSUM_TCP | CSUM_UDP |
|
|
CSUM_IP6_TCP | CSUM_IP6_UDP | CSUM_TSO);
|
|
mtd_desc_nr = M_HASHTYPE_GET(mbuf) != M_HASHTYPE_NONE ? 1 : 0;
|
|
tso_mss = is_tso ? mbuf->m_pkthdr.tso_segsz : 0;
|
|
|
|
eh = mtod(mbuf, struct ether_header *);
|
|
KASSERT(eh->ether_type != ETHERTYPE_VLAN,
|
|
("VLAN-tagged packets not supported"));
|
|
|
|
is_ipv6 = ntohs(eh->ether_type) == ETHERTYPE_IPV6;
|
|
l3_off = ETHER_HDR_LEN;
|
|
mbuf_next = m_getptr(mbuf, l3_off, &offset);
|
|
|
|
if (is_ipv6) {
|
|
ip6 = (struct ip6_hdr *)(mtodo(mbuf_next, offset));
|
|
l4_off = l3_off + sizeof(struct ip6_hdr);
|
|
is_tcp = (ip6->ip6_nxt == IPPROTO_TCP);
|
|
is_udp = (ip6->ip6_nxt == IPPROTO_UDP);
|
|
mbuf_next = m_getptr(mbuf, l4_off, &offset);
|
|
} else if (ntohs(eh->ether_type) == ETHERTYPE_IP) {
|
|
ip = (struct ip *)(mtodo(mbuf_next, offset));
|
|
l4_off = l3_off + (ip->ip_hl << 2);
|
|
is_tcp = (ip->ip_p == IPPROTO_TCP);
|
|
is_udp = (ip->ip_p == IPPROTO_UDP);
|
|
mbuf_next = m_getptr(mbuf, l4_off, &offset);
|
|
}
|
|
|
|
l4_data_off = 0;
|
|
if (is_tcp) {
|
|
th = (struct tcphdr *)(mtodo(mbuf_next, offset));
|
|
l4_data_off = l4_off + (th->th_off << 2);
|
|
} else if (is_udp)
|
|
l4_data_off = l4_off + sizeof(struct udphdr);
|
|
|
|
if (has_csum_flag) {
|
|
if ((csum_flags & (CSUM_TSO | CSUM_TCP | CSUM_IP6_TCP)) != 0)
|
|
csum_offset = offsetof(struct tcphdr, th_sum);
|
|
else
|
|
csum_offset = offsetof(struct udphdr, uh_sum);
|
|
}
|
|
|
|
/*
|
|
* If this packet is neither a TCP nor a UDP packet, the first segment,
|
|
* the one represented by the packet descriptor, will carry the
|
|
* spec-stipulated minimum of 182B.
|
|
*/
|
|
if (l4_data_off != 0)
|
|
first_seg_len = l4_data_off;
|
|
else
|
|
first_seg_len = MIN(pkt_len, GVE_GQ_TX_MIN_PKT_DESC_BYTES);
|
|
|
|
bytes_required = gve_fifo_bytes_required(tx, first_seg_len, pkt_len);
|
|
if (__predict_false(!gve_can_tx(tx, bytes_required))) {
|
|
counter_enter();
|
|
counter_u64_add_protected(tx->stats.tx_dropped_pkt_nospace_device, 1);
|
|
counter_u64_add_protected(tx->stats.tx_dropped_pkt, 1);
|
|
counter_exit();
|
|
return (ENOBUFS);
|
|
}
|
|
|
|
/* So that the cleanup taskqueue can free the mbuf eventually. */
|
|
info->mbuf = mbuf;
|
|
|
|
/*
|
|
* We don't want to split the header, so if necessary, pad to the end
|
|
* of the fifo and then put the header at the beginning of the fifo.
|
|
*/
|
|
pad_bytes = gve_tx_fifo_pad_alloc_one_frag(&tx->fifo, first_seg_len);
|
|
hdr_nfrags = gve_tx_alloc_fifo(&tx->fifo, first_seg_len + pad_bytes,
|
|
&info->iov[0]);
|
|
KASSERT(hdr_nfrags > 0, ("Number of header fragments for gve tx is 0"));
|
|
payload_nfrags = gve_tx_alloc_fifo(&tx->fifo, pkt_len - first_seg_len,
|
|
&info->iov[payload_iov]);
|
|
|
|
pkt_desc = &tx->desc_ring[idx].pkt;
|
|
gve_tx_fill_pkt_desc(pkt_desc, is_tso, l4_off,
|
|
1 + mtd_desc_nr + payload_nfrags, first_seg_len,
|
|
info->iov[hdr_nfrags - 1].iov_offset, has_csum_flag, csum_offset,
|
|
pkt_len);
|
|
|
|
m_copydata(mbuf, 0, first_seg_len,
|
|
(char *)tx->fifo.base + info->iov[hdr_nfrags - 1].iov_offset);
|
|
gve_dma_sync_for_device(tx->com.qpl,
|
|
info->iov[hdr_nfrags - 1].iov_offset,
|
|
info->iov[hdr_nfrags - 1].iov_len);
|
|
copy_offset = first_seg_len;
|
|
|
|
if (mtd_desc_nr == 1) {
|
|
next_idx = (tx->req + 1) & tx->mask;
|
|
mtd_desc = &tx->desc_ring[next_idx].mtd;
|
|
gve_tx_fill_mtd_desc(mtd_desc, mbuf);
|
|
}
|
|
|
|
for (i = payload_iov; i < payload_nfrags + payload_iov; i++) {
|
|
next_idx = (tx->req + 1 + mtd_desc_nr + i - payload_iov) & tx->mask;
|
|
seg_desc = &tx->desc_ring[next_idx].seg;
|
|
|
|
gve_tx_fill_seg_desc(seg_desc, is_tso, info->iov[i].iov_len,
|
|
info->iov[i].iov_offset, is_ipv6, l3_off, tso_mss);
|
|
|
|
m_copydata(mbuf, copy_offset, info->iov[i].iov_len,
|
|
(char *)tx->fifo.base + info->iov[i].iov_offset);
|
|
gve_dma_sync_for_device(tx->com.qpl,
|
|
info->iov[i].iov_offset, info->iov[i].iov_len);
|
|
copy_offset += info->iov[i].iov_len;
|
|
}
|
|
|
|
tx->req += (1 + mtd_desc_nr + payload_nfrags);
|
|
if (is_tso) {
|
|
counter_enter();
|
|
counter_u64_add_protected(tx->stats.tso_packet_cnt, 1);
|
|
counter_exit();
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
gve_xmit_br(struct gve_tx_ring *tx)
|
|
{
|
|
struct gve_priv *priv = tx->com.priv;
|
|
struct ifnet *ifp = priv->ifp;
|
|
struct mbuf *mbuf;
|
|
|
|
while ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 &&
|
|
(mbuf = drbr_peek(ifp, tx->br)) != NULL) {
|
|
|
|
if (__predict_false(gve_xmit(tx, mbuf) != 0)) {
|
|
drbr_putback(ifp, tx->br, mbuf);
|
|
taskqueue_enqueue(tx->xmit_tq, &tx->xmit_task);
|
|
break;
|
|
}
|
|
|
|
drbr_advance(ifp, tx->br);
|
|
BPF_MTAP(ifp, mbuf);
|
|
|
|
bus_dmamap_sync(tx->desc_ring_mem.tag, tx->desc_ring_mem.map,
|
|
BUS_DMASYNC_PREWRITE);
|
|
gve_db_bar_write_4(priv, tx->com.db_offset, tx->req);
|
|
}
|
|
}
|
|
|
|
void
|
|
gve_xmit_tq(void *arg, int pending)
|
|
{
|
|
struct gve_tx_ring *tx = (struct gve_tx_ring *)arg;
|
|
|
|
GVE_RING_LOCK(tx);
|
|
gve_xmit_br(tx);
|
|
GVE_RING_UNLOCK(tx);
|
|
}
|
|
|
|
static bool
|
|
is_vlan_tagged_pkt(struct mbuf *mbuf)
|
|
{
|
|
struct ether_header *eh;
|
|
|
|
eh = mtod(mbuf, struct ether_header *);
|
|
return (ntohs(eh->ether_type) == ETHERTYPE_VLAN);
|
|
}
|
|
|
|
int
|
|
gve_xmit_ifp(if_t ifp, struct mbuf *mbuf)
|
|
{
|
|
struct gve_priv *priv = if_getsoftc(ifp);
|
|
struct gve_tx_ring *tx;
|
|
bool is_br_empty;
|
|
int err;
|
|
uint32_t i;
|
|
|
|
if (__predict_false((if_getdrvflags(priv->ifp) & IFF_DRV_RUNNING) == 0))
|
|
return (ENODEV);
|
|
|
|
if (M_HASHTYPE_GET(mbuf) != M_HASHTYPE_NONE)
|
|
i = mbuf->m_pkthdr.flowid % priv->tx_cfg.num_queues;
|
|
else
|
|
i = curcpu % priv->tx_cfg.num_queues;
|
|
tx = &priv->tx[i];
|
|
|
|
if (__predict_false(is_vlan_tagged_pkt(mbuf))) {
|
|
counter_enter();
|
|
counter_u64_add_protected(tx->stats.tx_dropped_pkt_vlan, 1);
|
|
counter_u64_add_protected(tx->stats.tx_dropped_pkt, 1);
|
|
counter_exit();
|
|
m_freem(mbuf);
|
|
return (ENODEV);
|
|
}
|
|
|
|
is_br_empty = drbr_empty(ifp, tx->br);
|
|
err = drbr_enqueue(ifp, tx->br, mbuf);
|
|
if (__predict_false(err != 0)) {
|
|
taskqueue_enqueue(tx->xmit_tq, &tx->xmit_task);
|
|
counter_enter();
|
|
counter_u64_add_protected(tx->stats.tx_dropped_pkt_nospace_bufring, 1);
|
|
counter_u64_add_protected(tx->stats.tx_dropped_pkt, 1);
|
|
counter_exit();
|
|
return (err);
|
|
}
|
|
|
|
/*
|
|
* If the mbuf we just enqueued is the only one on the ring, then
|
|
* transmit it right away in the interests of low latency.
|
|
*/
|
|
if (is_br_empty && (GVE_RING_TRYLOCK(tx) != 0)) {
|
|
gve_xmit_br(tx);
|
|
GVE_RING_UNLOCK(tx);
|
|
} else {
|
|
taskqueue_enqueue(tx->xmit_tq, &tx->xmit_task);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
gve_qflush(if_t ifp)
|
|
{
|
|
struct gve_priv *priv = if_getsoftc(ifp);
|
|
struct gve_tx_ring *tx;
|
|
int i;
|
|
|
|
for (i = 0; i < priv->tx_cfg.num_queues; ++i) {
|
|
tx = &priv->tx[i];
|
|
if (drbr_empty(ifp, tx->br) == 0) {
|
|
GVE_RING_LOCK(tx);
|
|
drbr_flush(ifp, tx->br);
|
|
GVE_RING_UNLOCK(tx);
|
|
}
|
|
}
|
|
|
|
if_qflush(ifp);
|
|
}
|