616 lines
14 KiB
C
616 lines
14 KiB
C
/*-
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* Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by the University of Cambridge Computer
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* Laboratory with support from ARM Ltd.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <machine/pmc_mdep.h>
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#include <machine/cpu.h>
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#include "opt_acpi.h"
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static int arm64_npmcs;
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struct arm64_event_code_map {
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enum pmc_event pe_ev;
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uint8_t pe_code;
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};
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/*
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* Per-processor information.
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*/
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struct arm64_cpu {
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struct pmc_hw *pc_arm64pmcs;
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};
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static struct arm64_cpu **arm64_pcpu;
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/*
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* Interrupt Enable Set Register
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*/
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static __inline void
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arm64_interrupt_enable(uint32_t pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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WRITE_SPECIALREG(pmintenset_el1, reg);
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isb();
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}
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/*
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* Interrupt Clear Set Register
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*/
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static __inline void
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arm64_interrupt_disable(uint32_t pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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WRITE_SPECIALREG(pmintenclr_el1, reg);
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isb();
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}
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/*
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* Counter Set Enable Register
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*/
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static __inline void
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arm64_counter_enable(unsigned int pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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WRITE_SPECIALREG(pmcntenset_el0, reg);
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isb();
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}
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/*
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* Counter Clear Enable Register
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*/
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static __inline void
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arm64_counter_disable(unsigned int pmc)
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{
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uint32_t reg;
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reg = (1 << pmc);
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WRITE_SPECIALREG(pmcntenclr_el0, reg);
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isb();
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}
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/*
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* Performance Monitors Control Register
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*/
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static uint32_t
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arm64_pmcr_read(void)
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{
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uint32_t reg;
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reg = READ_SPECIALREG(pmcr_el0);
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return (reg);
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}
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static void
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arm64_pmcr_write(uint32_t reg)
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{
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WRITE_SPECIALREG(pmcr_el0, reg);
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isb();
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}
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/*
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* Performance Count Register N
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*/
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static uint32_t
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arm64_pmcn_read(unsigned int pmc)
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{
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KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
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WRITE_SPECIALREG(pmselr_el0, pmc);
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isb();
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return (READ_SPECIALREG(pmxevcntr_el0));
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}
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static void
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arm64_pmcn_write(unsigned int pmc, uint32_t reg)
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{
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KASSERT(pmc < arm64_npmcs, ("%s: illegal PMC number %d", __func__, pmc));
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WRITE_SPECIALREG(pmselr_el0, pmc);
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WRITE_SPECIALREG(pmxevcntr_el0, reg);
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isb();
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}
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static int
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arm64_allocate_pmc(int cpu, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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uint32_t config;
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enum pmc_event pe;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] illegal row index %d", __LINE__, ri));
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if (a->pm_class != PMC_CLASS_ARMV8) {
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return (EINVAL);
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}
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pe = a->pm_ev;
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/* Adjust the config value if needed. */
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config = a->pm_md.pm_md_config;
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if ((a->pm_md.pm_md_flags & PM_MD_RAW_EVENT) == 0) {
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config = (uint32_t)pe - PMC_EV_ARMV8_FIRST;
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if (config > (PMC_EV_ARMV8_LAST - PMC_EV_ARMV8_FIRST))
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return (EINVAL);
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}
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switch (a->pm_caps & (PMC_CAP_SYSTEM | PMC_CAP_USER)) {
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case PMC_CAP_SYSTEM:
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config |= PMEVTYPER_U;
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break;
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case PMC_CAP_USER:
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config |= PMEVTYPER_P;
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break;
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default:
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/*
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* Trace both USER and SYSTEM if none are specified
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* (default setting) or if both flags are specified
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* (user explicitly requested both qualifiers).
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*/
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break;
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}
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pm->pm_md.pm_arm64.pm_arm64_evsel = config;
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PMCDBG2(MDP, ALL, 2, "arm64-allocate ri=%d -> config=0x%x", ri, config);
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return (0);
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}
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static int
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arm64_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v)
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{
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pmc_value_t tmp;
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register_t s;
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int reg;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] illegal row index %d", __LINE__, ri));
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/*
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* Ensure we don't get interrupted while updating the overflow count.
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*/
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s = intr_disable();
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tmp = arm64_pmcn_read(ri);
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reg = (1 << ri);
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if ((READ_SPECIALREG(pmovsclr_el0) & reg) != 0) {
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/* Clear Overflow Flag */
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WRITE_SPECIALREG(pmovsclr_el0, reg);
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pm->pm_pcpu_state[cpu].pps_overflowcnt++;
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/* Reread counter in case we raced. */
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tmp = arm64_pmcn_read(ri);
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}
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tmp += 0x100000000llu * pm->pm_pcpu_state[cpu].pps_overflowcnt;
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intr_restore(s);
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PMCDBG2(MDP, REA, 2, "arm64-read id=%d -> %jd", ri, tmp);
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
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/*
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* Clamp value to 0 if the counter just overflowed,
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* otherwise the returned reload count would wrap to a
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* huge value.
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*/
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if ((tmp & (1ull << 63)) == 0)
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tmp = 0;
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else
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tmp = ARMV8_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp);
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}
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*v = tmp;
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return (0);
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}
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static int
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arm64_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v)
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{
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] illegal row-index %d", __LINE__, ri));
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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v = ARMV8_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
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PMCDBG3(MDP, WRI, 1, "arm64-write cpu=%d ri=%d v=%jx", cpu, ri, v);
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pm->pm_pcpu_state[cpu].pps_overflowcnt = v >> 32;
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arm64_pmcn_write(ri, v);
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return (0);
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}
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static int
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arm64_config_pmc(int cpu, int ri, struct pmc *pm)
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{
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struct pmc_hw *phw;
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PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] illegal row-index %d", __LINE__, ri));
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phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
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KASSERT(pm == NULL || phw->phw_pmc == NULL,
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("[arm64,%d] pm=%p phw->pm=%p hwpmc not unconfigured",
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__LINE__, pm, phw->phw_pmc));
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phw->phw_pmc = pm;
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return (0);
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}
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static int
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arm64_start_pmc(int cpu, int ri, struct pmc *pm)
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{
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uint32_t config;
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config = pm->pm_md.pm_arm64.pm_arm64_evsel;
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/*
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* Configure the event selection.
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*/
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WRITE_SPECIALREG(pmselr_el0, ri);
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WRITE_SPECIALREG(pmxevtyper_el0, config);
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isb();
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/*
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* Enable the PMC.
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*/
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arm64_interrupt_enable(ri);
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arm64_counter_enable(ri);
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return (0);
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}
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static int
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arm64_stop_pmc(int cpu, int ri, struct pmc *pm __unused)
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{
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/*
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* Disable the PMCs.
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*/
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arm64_counter_disable(ri);
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arm64_interrupt_disable(ri);
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return (0);
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}
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static int
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arm64_release_pmc(int cpu, int ri, struct pmc *pmc)
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{
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struct pmc_hw *phw __diagused;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] illegal row-index %d", __LINE__, ri));
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phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
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KASSERT(phw->phw_pmc == NULL,
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("[arm64,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
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return (0);
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}
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static int
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arm64_intr(struct trapframe *tf)
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{
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int retval, ri;
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struct pmc *pm;
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int error;
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int reg, cpu;
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cpu = curcpu;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] CPU %d out of range", __LINE__, cpu));
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PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *)tf,
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TRAPF_USERMODE(tf));
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retval = 0;
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for (ri = 0; ri < arm64_npmcs; ri++) {
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pm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
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if (pm == NULL)
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continue;
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/* Check if counter is overflowed */
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reg = (1 << ri);
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if ((READ_SPECIALREG(pmovsclr_el0) & reg) == 0)
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continue;
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/* Clear Overflow Flag */
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WRITE_SPECIALREG(pmovsclr_el0, reg);
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isb();
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retval = 1; /* Found an interrupting PMC. */
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pm->pm_pcpu_state[cpu].pps_overflowcnt += 1;
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if (!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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continue;
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if (pm->pm_state != PMC_STATE_RUNNING)
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continue;
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error = pmc_process_interrupt(PMC_HR, pm, tf);
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if (error)
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arm64_stop_pmc(cpu, ri, pm);
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/* Reload sampling count */
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arm64_write_pmc(cpu, ri, pm, pm->pm_sc.pm_reloadcount);
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}
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return (retval);
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}
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static int
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arm64_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
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{
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struct pmc_hw *phw;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d], illegal CPU %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < arm64_npmcs,
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("[arm64,%d] row-index %d out of range", __LINE__, ri));
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phw = &arm64_pcpu[cpu]->pc_arm64pmcs[ri];
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snprintf(pi->pm_name, sizeof(pi->pm_name), "ARMV8-%d", ri);
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pi->pm_class = PMC_CLASS_ARMV8;
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if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
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pi->pm_enabled = TRUE;
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*ppmc = phw->phw_pmc;
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} else {
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pi->pm_enabled = FALSE;
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*ppmc = NULL;
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}
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return (0);
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}
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static int
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arm64_get_config(int cpu, int ri, struct pmc **ppm)
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{
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*ppm = arm64_pcpu[cpu]->pc_arm64pmcs[ri].phw_pmc;
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return (0);
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}
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static int
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arm64_pcpu_init(struct pmc_mdep *md, int cpu)
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{
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struct arm64_cpu *pac;
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struct pmc_hw *phw;
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struct pmc_cpu *pc;
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uint64_t pmcr;
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int first_ri;
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int i;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[arm64,%d] wrong cpu number %d", __LINE__, cpu));
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PMCDBG0(MDP, INI, 1, "arm64-pcpu-init");
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arm64_pcpu[cpu] = pac = malloc(sizeof(struct arm64_cpu), M_PMC,
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M_WAITOK | M_ZERO);
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pac->pc_arm64pmcs = malloc(sizeof(struct pmc_hw) * arm64_npmcs,
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M_PMC, M_WAITOK | M_ZERO);
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pc = pmc_pcpu[cpu];
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first_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8].pcd_ri;
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KASSERT(pc != NULL, ("[arm64,%d] NULL per-cpu pointer", __LINE__));
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for (i = 0, phw = pac->pc_arm64pmcs; i < arm64_npmcs; i++, phw++) {
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phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
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PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(i);
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phw->phw_pmc = NULL;
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pc->pc_hwpmcs[i + first_ri] = phw;
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}
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/*
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* Disable all counters and overflow interrupts. Upon reset they are in
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* an undefined state.
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*
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* Don't issue an isb here, just wait for the one in arm64_pmcr_write()
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* to make the writes visible.
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*/
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WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff);
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WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff);
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/* Enable unit */
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pmcr = arm64_pmcr_read();
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pmcr |= PMCR_E;
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arm64_pmcr_write(pmcr);
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return (0);
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}
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static int
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arm64_pcpu_fini(struct pmc_mdep *md, int cpu)
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{
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uint32_t pmcr;
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PMCDBG0(MDP, INI, 1, "arm64-pcpu-fini");
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pmcr = arm64_pmcr_read();
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pmcr &= ~PMCR_E;
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arm64_pmcr_write(pmcr);
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free(arm64_pcpu[cpu]->pc_arm64pmcs, M_PMC);
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free(arm64_pcpu[cpu], M_PMC);
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arm64_pcpu[cpu] = NULL;
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return (0);
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}
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struct pmc_mdep *
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pmc_arm64_initialize(void)
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{
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struct pmc_mdep *pmc_mdep;
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struct pmc_classdep *pcd;
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int classes, idcode, impcode;
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int reg;
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uint64_t midr;
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reg = arm64_pmcr_read();
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arm64_npmcs = (reg & PMCR_N_MASK) >> PMCR_N_SHIFT;
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impcode = (reg & PMCR_IMP_MASK) >> PMCR_IMP_SHIFT;
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idcode = (reg & PMCR_IDCODE_MASK) >> PMCR_IDCODE_SHIFT;
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PMCDBG1(MDP, INI, 1, "arm64-init npmcs=%d", arm64_npmcs);
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/*
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* Write the CPU model to kern.hwpmc.cpuid.
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*
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* We zero the variant and revision fields.
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*
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* TODO: how to handle differences between cores due to big.LITTLE?
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* For now, just use MIDR from CPU 0.
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*/
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midr = (uint64_t)(pcpu_find(0)->pc_midr);
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midr &= ~(CPU_VAR_MASK | CPU_REV_MASK);
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snprintf(pmc_cpuid, sizeof(pmc_cpuid), "0x%016lx", midr);
|
|
|
|
/*
|
|
* Allocate space for pointers to PMC HW descriptors and for
|
|
* the MDEP structure used by MI code.
|
|
*/
|
|
arm64_pcpu = malloc(sizeof(struct arm64_cpu *) * pmc_cpu_max(),
|
|
M_PMC, M_WAITOK | M_ZERO);
|
|
|
|
/* One AArch64 CPU class */
|
|
classes = 1;
|
|
|
|
#ifdef DEV_ACPI
|
|
/* Query presence of optional classes and set max class. */
|
|
if (pmc_cmn600_nclasses() > 0)
|
|
classes = MAX(classes, PMC_MDEP_CLASS_INDEX_CMN600);
|
|
if (pmc_dmc620_nclasses() > 0)
|
|
classes = MAX(classes, PMC_MDEP_CLASS_INDEX_DMC620_C);
|
|
#endif
|
|
|
|
pmc_mdep = pmc_mdep_alloc(classes);
|
|
|
|
switch(impcode) {
|
|
case PMCR_IMP_ARM:
|
|
switch (idcode) {
|
|
case PMCR_IDCODE_CORTEX_A76:
|
|
case PMCR_IDCODE_NEOVERSE_N1:
|
|
pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A76;
|
|
break;
|
|
case PMCR_IDCODE_CORTEX_A57:
|
|
case PMCR_IDCODE_CORTEX_A72:
|
|
pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A57;
|
|
break;
|
|
default:
|
|
case PMCR_IDCODE_CORTEX_A53:
|
|
pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
pmc_mdep->pmd_cputype = PMC_CPU_ARMV8_CORTEX_A53;
|
|
break;
|
|
}
|
|
|
|
pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_ARMV8];
|
|
pcd->pcd_caps = ARMV8_PMC_CAPS;
|
|
pcd->pcd_class = PMC_CLASS_ARMV8;
|
|
pcd->pcd_num = arm64_npmcs;
|
|
pcd->pcd_ri = pmc_mdep->pmd_npmc;
|
|
pcd->pcd_width = 32;
|
|
|
|
pcd->pcd_allocate_pmc = arm64_allocate_pmc;
|
|
pcd->pcd_config_pmc = arm64_config_pmc;
|
|
pcd->pcd_pcpu_fini = arm64_pcpu_fini;
|
|
pcd->pcd_pcpu_init = arm64_pcpu_init;
|
|
pcd->pcd_describe = arm64_describe;
|
|
pcd->pcd_get_config = arm64_get_config;
|
|
pcd->pcd_read_pmc = arm64_read_pmc;
|
|
pcd->pcd_release_pmc = arm64_release_pmc;
|
|
pcd->pcd_start_pmc = arm64_start_pmc;
|
|
pcd->pcd_stop_pmc = arm64_stop_pmc;
|
|
pcd->pcd_write_pmc = arm64_write_pmc;
|
|
|
|
pmc_mdep->pmd_intr = arm64_intr;
|
|
pmc_mdep->pmd_npmc += arm64_npmcs;
|
|
|
|
#ifdef DEV_ACPI
|
|
if (pmc_cmn600_nclasses() > 0)
|
|
pmc_cmn600_initialize(pmc_mdep);
|
|
if (pmc_dmc620_nclasses() > 0) {
|
|
pmc_dmc620_initialize_cd2(pmc_mdep);
|
|
pmc_dmc620_initialize_c(pmc_mdep);
|
|
}
|
|
#endif
|
|
|
|
return (pmc_mdep);
|
|
}
|
|
|
|
void
|
|
pmc_arm64_finalize(struct pmc_mdep *md)
|
|
{
|
|
PMCDBG0(MDP, INI, 1, "arm64-finalize");
|
|
|
|
free(arm64_pcpu, M_PMC);
|
|
}
|