385 lines
9.8 KiB
C
385 lines
9.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2013 Justin Hibbits
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <sys/systm.h>
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#include <machine/pmc_mdep.h>
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#include <machine/spr.h>
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#include <machine/cpu.h>
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#include "hwpmc_powerpc.h"
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#define PPC970_MAX_PMCS 8
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#define PMC_PPC970_FLAG_PMCS 0x000000ff
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/* MMCR0, PMC1 is 8 bytes in, PMC2 is 1 byte in. */
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#define PPC970_SET_MMCR0_PMCSEL(r, x, i) \
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((r & ~(0x1f << (7 * (1 - i) + 1))) | (x << (7 * (1 - i) + 1)))
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/* MMCR1 has 6 PMC*SEL items (PMC3->PMC8), in sequence. */
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#define PPC970_SET_MMCR1_PMCSEL(r, x, i) \
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((r & ~(0x1f << (5 * (7 - i) + 2))) | (x << (5 * (7 - i) + 2)))
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/* How PMC works on PPC970:
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*
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* Any PMC can count a direct event. Indirect events are handled specially.
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* Direct events: As published.
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*
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* Encoding 00 000 -- Add byte lane bit counters
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* MMCR1[24:31] -- select bit matching PMC being an adder.
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* Bus events:
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* PMCxSEL: 1x -- select from byte lane: 10 == lower lane (0/1), 11 == upper
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* lane (2/3).
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* PMCxSEL[2:4] -- bit in the byte lane selected.
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*
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* PMC[1,2,5,6] == lane 0/lane 2
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* PMC[3,4,7,8] == lane 1,3
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*
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*
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* Lanes:
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* Lane 0 -- TTM0(FPU,ISU,IFU,VPU)
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* TTM1(IDU,ISU,STS)
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* LSU0 byte 0
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* LSU1 byte 0
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* Lane 1 -- TTM0
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* TTM1
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* LSU0 byte 1
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* LSU1 byte 1
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* Lane 2 -- TTM0
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* TTM1
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* LSU0 byte 2
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* LSU1 byte 2 or byte 6
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* Lane 3 -- TTM0
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* TTM1
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* LSU0 byte 3
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* LSU1 byte 3 or byte 7
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*
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* Adders:
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* Add byte lane for PMC (above), bit 0+4, 1+5, 2+6, 3+7
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*/
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static struct pmc_ppc_event ppc970_event_codes[] = {
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{PMC_EV_PPC970_INSTR_COMPLETED,
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.pe_flags = PMC_PPC970_FLAG_PMCS,
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.pe_code = 0x09
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},
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{PMC_EV_PPC970_MARKED_GROUP_DISPATCH,
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.pe_flags = PMC_FLAG_PMC1,
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.pe_code = 0x2
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},
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{PMC_EV_PPC970_MARKED_STORE_COMPLETED,
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.pe_flags = PMC_FLAG_PMC1,
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.pe_code = 0x03
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},
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{PMC_EV_PPC970_GCT_EMPTY,
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.pe_flags = PMC_FLAG_PMC1,
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.pe_code = 0x04
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},
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{PMC_EV_PPC970_RUN_CYCLES,
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.pe_flags = PMC_FLAG_PMC1,
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.pe_code = 0x05
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},
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{PMC_EV_PPC970_OVERFLOW,
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.pe_flags = PMC_PPC970_FLAG_PMCS,
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.pe_code = 0x0a
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},
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{PMC_EV_PPC970_CYCLES,
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.pe_flags = PMC_PPC970_FLAG_PMCS,
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.pe_code = 0x0f
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},
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{PMC_EV_PPC970_THRESHOLD_TIMEOUT,
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.pe_flags = PMC_FLAG_PMC2,
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.pe_code = 0x3
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},
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{PMC_EV_PPC970_GROUP_DISPATCH,
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.pe_flags = PMC_FLAG_PMC2,
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.pe_code = 0x4
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},
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{PMC_EV_PPC970_BR_MARKED_INSTR_FINISH,
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.pe_flags = PMC_FLAG_PMC2,
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.pe_code = 0x5
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},
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{PMC_EV_PPC970_GCT_EMPTY_BY_SRQ_FULL,
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.pe_flags = PMC_FLAG_PMC2,
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.pe_code = 0xb
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},
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{PMC_EV_PPC970_STOP_COMPLETION,
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.pe_flags = PMC_FLAG_PMC3,
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.pe_code = 0x1
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},
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{PMC_EV_PPC970_LSU_EMPTY,
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.pe_flags = PMC_FLAG_PMC3,
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.pe_code = 0x2
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},
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{PMC_EV_PPC970_MARKED_STORE_WITH_INTR,
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.pe_flags = PMC_FLAG_PMC3,
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.pe_code = 0x3
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},
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{PMC_EV_PPC970_CYCLES_IN_SUPER,
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.pe_flags = PMC_FLAG_PMC3,
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.pe_code = 0x4
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},
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{PMC_EV_PPC970_VPU_MARKED_INSTR_COMPLETED,
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.pe_flags = PMC_FLAG_PMC3,
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.pe_code = 0x5
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},
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{PMC_EV_PPC970_FXU0_IDLE_FXU1_BUSY,
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.pe_flags = PMC_FLAG_PMC4,
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.pe_code = 0x2
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},
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{PMC_EV_PPC970_SRQ_EMPTY,
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.pe_flags = PMC_FLAG_PMC4,
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.pe_code = 0x3
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},
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{PMC_EV_PPC970_MARKED_GROUP_COMPLETED,
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.pe_flags = PMC_FLAG_PMC4,
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.pe_code = 0x4
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},
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{PMC_EV_PPC970_CR_MARKED_INSTR_FINISH,
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.pe_flags = PMC_FLAG_PMC4,
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.pe_code = 0x5
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},
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{PMC_EV_PPC970_DISPATCH_SUCCESS,
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.pe_flags = PMC_FLAG_PMC5,
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.pe_code = 0x1
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},
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{PMC_EV_PPC970_FXU0_IDLE_FXU1_IDLE,
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.pe_flags = PMC_FLAG_PMC5,
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.pe_code = 0x2
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},
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{PMC_EV_PPC970_ONE_PLUS_INSTR_COMPLETED,
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.pe_flags = PMC_FLAG_PMC5,
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.pe_code = 0x3
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},
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{PMC_EV_PPC970_GROUP_MARKED_IDU,
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.pe_flags = PMC_FLAG_PMC5,
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.pe_code = 0x4
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},
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{PMC_EV_PPC970_MARKED_GROUP_COMPLETE_TIMEOUT,
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.pe_flags = PMC_FLAG_PMC5,
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.pe_code = 0x5
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},
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{PMC_EV_PPC970_FXU0_BUSY_FXU1_BUSY,
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.pe_flags = PMC_FLAG_PMC6,
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.pe_code = 0x2
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},
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{PMC_EV_PPC970_MARKED_STORE_SENT_TO_STS,
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.pe_flags = PMC_FLAG_PMC6,
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.pe_code = 0x3
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},
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{PMC_EV_PPC970_FXU_MARKED_INSTR_FINISHED,
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.pe_flags = PMC_FLAG_PMC6,
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.pe_code = 0x4
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},
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{PMC_EV_PPC970_MARKED_GROUP_ISSUED,
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.pe_flags = PMC_FLAG_PMC6,
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.pe_code = 0x5
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},
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{PMC_EV_PPC970_FXU0_BUSY_FXU1_IDLE,
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.pe_flags = PMC_FLAG_PMC7,
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.pe_code = 0x2
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},
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{PMC_EV_PPC970_GROUP_COMPLETED,
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.pe_flags = PMC_FLAG_PMC7,
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.pe_code = 0x3
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},
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{PMC_EV_PPC970_FPU_MARKED_INSTR_COMPLETED,
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.pe_flags = PMC_FLAG_PMC7,
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.pe_code = 0x4
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},
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{PMC_EV_PPC970_MARKED_INSTR_FINISH_ANY_UNIT,
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.pe_flags = PMC_FLAG_PMC7,
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.pe_code = 0x5
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},
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{PMC_EV_PPC970_EXTERNAL_INTERRUPT,
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.pe_flags = PMC_FLAG_PMC8,
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.pe_code = 0x2
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},
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{PMC_EV_PPC970_GROUP_DISPATCH_REJECT,
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.pe_flags = PMC_FLAG_PMC8,
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.pe_code = 0x3
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},
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{PMC_EV_PPC970_LSU_MARKED_INSTR_FINISH,
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.pe_flags = PMC_FLAG_PMC8,
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.pe_code = 0x4
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},
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{PMC_EV_PPC970_TIMEBASE_EVENT,
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.pe_flags = PMC_FLAG_PMC8,
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.pe_code = 0x5
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},
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#if 0
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{PMC_EV_PPC970_LSU_COMPLETION_STALL, },
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{PMC_EV_PPC970_FXU_COMPLETION_STALL, },
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{PMC_EV_PPC970_DCACHE_MISS_COMPLETION_STALL, },
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{PMC_EV_PPC970_FPU_COMPLETION_STALL, },
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{PMC_EV_PPC970_FXU_LONG_INSTR_COMPLETION_STALL, },
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{PMC_EV_PPC970_REJECT_COMPLETION_STALL, },
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{PMC_EV_PPC970_FPU_LONG_INSTR_COMPLETION_STALL, },
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{PMC_EV_PPC970_GCT_EMPTY_BY_ICACHE_MISS, },
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{PMC_EV_PPC970_REJECT_COMPLETION_STALL_ERAT_MISS, },
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{PMC_EV_PPC970_GCT_EMPTY_BY_BRANCH_MISS_PREDICT, },
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#endif
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};
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static size_t ppc970_event_codes_size = nitems(ppc970_event_codes);
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static void
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ppc970_set_pmc(int cpu, int ri, int config)
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{
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register_t pmc_mmcr;
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int config_mask;
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if (config == PMCN_NONE)
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config = PMC970N_NONE;
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/*
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* The mask is inverted (enable is 1) compared to the flags in MMCR0,
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* which are Freeze flags.
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*/
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config_mask = ~config & POWERPC_PMC_ENABLE;
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config &= ~POWERPC_PMC_ENABLE;
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/*
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* Disable the PMCs.
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*/
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switch (ri) {
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case 0:
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case 1:
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pmc_mmcr = mfspr(SPR_MMCR0);
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pmc_mmcr = PPC970_SET_MMCR0_PMCSEL(pmc_mmcr, config, ri);
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mtspr(SPR_MMCR0, pmc_mmcr);
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break;
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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pmc_mmcr = mfspr(SPR_MMCR1);
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pmc_mmcr = PPC970_SET_MMCR1_PMCSEL(pmc_mmcr, config, ri);
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mtspr(SPR_MMCR1, pmc_mmcr);
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break;
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}
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if (config != PMC970N_NONE) {
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pmc_mmcr = mfspr(SPR_MMCR0);
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pmc_mmcr &= ~SPR_MMCR0_FC;
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pmc_mmcr |= config_mask;
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mtspr(SPR_MMCR0, pmc_mmcr);
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}
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}
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static int
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ppc970_pcpu_init(struct pmc_mdep *md, int cpu)
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{
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powerpc_pcpu_init(md, cpu);
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/* Clear the MMCRs, and set FC, to disable all PMCs. */
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/* 970 PMC is not counted when set to 0x08 */
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mtspr(SPR_MMCR0, SPR_MMCR0_FC | SPR_MMCR0_PMXE |
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SPR_MMCR0_FCECE | SPR_MMCR0_PMC1CE | SPR_MMCR0_PMCNCE |
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SPR_MMCR0_PMC1SEL(0x8) | SPR_MMCR0_PMC2SEL(0x8));
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mtspr(SPR_MMCR1, 0x4218420);
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return (0);
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}
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static int
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ppc970_pcpu_fini(struct pmc_mdep *md, int cpu)
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{
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register_t mmcr0;
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/* Freeze counters, disable interrupts */
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mmcr0 = mfspr(SPR_MMCR0);
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mmcr0 &= ~SPR_MMCR0_PMXE;
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mmcr0 |= SPR_MMCR0_FC;
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mtspr(SPR_MMCR0, mmcr0);
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return (powerpc_pcpu_fini(md, cpu));
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}
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static void
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ppc970_resume_pmc(bool ie)
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{
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register_t mmcr0;
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/* Unfreeze counters and re-enable PERF exceptions if requested. */
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mmcr0 = mfspr(SPR_MMCR0);
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mmcr0 &= ~(SPR_MMCR0_FC | SPR_MMCR0_PMXE);
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if (ie)
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mmcr0 |= SPR_MMCR0_PMXE;
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mtspr(SPR_MMCR0, mmcr0);
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}
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int
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pmc_ppc970_initialize(struct pmc_mdep *pmc_mdep)
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{
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struct pmc_classdep *pcd;
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pmc_mdep->pmd_cputype = PMC_CPU_PPC_970;
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pcd = &pmc_mdep->pmd_classdep[PMC_MDEP_CLASS_INDEX_POWERPC];
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pcd->pcd_caps = POWERPC_PMC_CAPS;
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pcd->pcd_class = PMC_CLASS_PPC970;
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pcd->pcd_num = PPC970_MAX_PMCS;
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pcd->pcd_ri = pmc_mdep->pmd_npmc;
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pcd->pcd_width = 32;
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pcd->pcd_allocate_pmc = powerpc_allocate_pmc;
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pcd->pcd_config_pmc = powerpc_config_pmc;
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pcd->pcd_pcpu_fini = ppc970_pcpu_fini;
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pcd->pcd_pcpu_init = ppc970_pcpu_init;
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pcd->pcd_describe = powerpc_describe;
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pcd->pcd_get_config = powerpc_get_config;
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pcd->pcd_read_pmc = powerpc_read_pmc;
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pcd->pcd_release_pmc = powerpc_release_pmc;
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pcd->pcd_start_pmc = powerpc_start_pmc;
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pcd->pcd_stop_pmc = powerpc_stop_pmc;
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pcd->pcd_write_pmc = powerpc_write_pmc;
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pmc_mdep->pmd_npmc += PPC970_MAX_PMCS;
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pmc_mdep->pmd_intr = powerpc_pmc_intr;
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ppc_event_codes = ppc970_event_codes;
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ppc_event_codes_size = ppc970_event_codes_size;
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ppc_event_first = PMC_EV_PPC970_FIRST;
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ppc_event_last = PMC_EV_PPC970_LAST;
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ppc_max_pmcs = PPC970_MAX_PMCS;
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ppc_class = pcd->pcd_class;
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powerpc_set_pmc = ppc970_set_pmc;
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powerpc_pmcn_read = powerpc_pmcn_read_default;
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powerpc_pmcn_write = powerpc_pmcn_write_default;
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powerpc_resume_pmc = ppc970_resume_pmc;
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return (0);
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}
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