758 lines
18 KiB
C
758 lines
18 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2010 Fabien Thomas
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Intel Uncore PMCs.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/pmc.h>
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#include <sys/pmckern.h>
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#include <sys/systm.h>
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#include <machine/intr_machdep.h>
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#include <x86/apicvar.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/specialreg.h>
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#define UCF_PMC_CAPS \
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(PMC_CAP_READ | PMC_CAP_WRITE)
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#define UCP_PMC_CAPS \
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(PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \
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PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE)
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#define SELECTSEL(x) \
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(((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \
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UCP_CB0_EVSEL0 : UCP_EVSEL0)
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#define SELECTOFF(x) \
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(((x) == PMC_CPU_INTEL_SANDYBRIDGE || (x) == PMC_CPU_INTEL_HASWELL) ? \
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UCF_OFFSET_SB : UCF_OFFSET)
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static enum pmc_cputype uncore_cputype;
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struct uncore_cpu {
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volatile uint32_t pc_ucfctrl; /* Fixed function control. */
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volatile uint64_t pc_globalctrl; /* Global control register. */
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struct pmc_hw pc_uncorepmcs[];
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};
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static struct uncore_cpu **uncore_pcpu;
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static uint64_t uncore_pmcmask;
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static int uncore_ucf_ri; /* relative index of fixed counters */
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static int uncore_ucf_width;
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static int uncore_ucf_npmc;
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static int uncore_ucp_width;
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static int uncore_ucp_npmc;
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static int
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uncore_pcpu_noop(struct pmc_mdep *md, int cpu)
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{
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(void) md;
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(void) cpu;
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return (0);
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}
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static int
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uncore_pcpu_init(struct pmc_mdep *md, int cpu)
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{
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struct pmc_cpu *pc;
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struct uncore_cpu *cc;
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struct pmc_hw *phw;
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int uncore_ri, n, npmc;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[ucf,%d] insane cpu number %d", __LINE__, cpu));
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PMCDBG1(MDP,INI,1,"uncore-init cpu=%d", cpu);
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uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri;
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npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num;
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npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num;
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cc = malloc(sizeof(struct uncore_cpu) + npmc * sizeof(struct pmc_hw),
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M_PMC, M_WAITOK | M_ZERO);
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uncore_pcpu[cpu] = cc;
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pc = pmc_pcpu[cpu];
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KASSERT(pc != NULL && cc != NULL,
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("[uncore,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu));
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for (n = 0, phw = cc->pc_uncorepmcs; n < npmc; n++, phw++) {
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phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
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PMC_PHW_CPU_TO_STATE(cpu) |
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PMC_PHW_INDEX_TO_STATE(n + uncore_ri);
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phw->phw_pmc = NULL;
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pc->pc_hwpmcs[n + uncore_ri] = phw;
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}
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return (0);
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}
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static int
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uncore_pcpu_fini(struct pmc_mdep *md, int cpu)
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{
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int uncore_ri, n, npmc;
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struct pmc_cpu *pc;
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struct uncore_cpu *cc;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[uncore,%d] insane cpu number (%d)", __LINE__, cpu));
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PMCDBG1(MDP,INI,1,"uncore-pcpu-fini cpu=%d", cpu);
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if ((cc = uncore_pcpu[cpu]) == NULL)
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return (0);
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uncore_pcpu[cpu] = NULL;
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pc = pmc_pcpu[cpu];
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KASSERT(pc != NULL, ("[uncore,%d] NULL per-cpu %d state", __LINE__,
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cpu));
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npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_num;
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uncore_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP].pcd_ri;
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for (n = 0; n < npmc; n++)
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wrmsr(SELECTSEL(uncore_cputype) + n, 0);
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wrmsr(UCF_CTRL, 0);
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npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF].pcd_num;
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for (n = 0; n < npmc; n++)
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pc->pc_hwpmcs[n + uncore_ri] = NULL;
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free(cc, M_PMC);
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return (0);
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}
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/*
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* Fixed function counters.
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*/
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static pmc_value_t
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ucf_perfctr_value_to_reload_count(pmc_value_t v)
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{
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/* If the PMC has overflowed, return a reload count of zero. */
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if ((v & (1ULL << (uncore_ucf_width - 1))) == 0)
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return (0);
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v &= (1ULL << uncore_ucf_width) - 1;
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return (1ULL << uncore_ucf_width) - v;
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}
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static pmc_value_t
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ucf_reload_count_to_perfctr_value(pmc_value_t rlc)
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{
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return (1ULL << uncore_ucf_width) - rlc;
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}
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static int
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ucf_allocate_pmc(int cpu, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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uint32_t flags;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[uncore,%d] illegal CPU %d", __LINE__, cpu));
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PMCDBG2(MDP,ALL,1, "ucf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps);
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if (ri < 0 || ri > uncore_ucf_npmc)
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return (EINVAL);
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if (a->pm_class != PMC_CLASS_UCF)
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return (EINVAL);
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flags = UCF_EN;
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pm->pm_md.pm_ucf.pm_ucf_ctrl = (flags << (ri * 4));
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PMCDBG1(MDP,ALL,2, "ucf-allocate config=0x%jx",
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(uintmax_t) pm->pm_md.pm_ucf.pm_ucf_ctrl);
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return (0);
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}
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static int
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ucf_config_pmc(int cpu, int ri, struct pmc *pm)
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{
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[uncore,%d] illegal CPU %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
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("[uncore,%d] illegal row-index %d", __LINE__, ri));
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PMCDBG3(MDP,CFG,1, "ucf-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
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KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__,
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cpu));
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uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc = pm;
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return (0);
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}
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static int
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ucf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
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{
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struct pmc_hw *phw;
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phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri];
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snprintf(pi->pm_name, sizeof(pi->pm_name), "UCF-%d", ri);
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pi->pm_class = PMC_CLASS_UCF;
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if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
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pi->pm_enabled = TRUE;
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*ppmc = phw->phw_pmc;
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} else {
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pi->pm_enabled = FALSE;
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*ppmc = NULL;
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}
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return (0);
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}
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static int
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ucf_get_config(int cpu, int ri, struct pmc **ppm)
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{
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*ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc;
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return (0);
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}
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static int
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ucf_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v)
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{
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pmc_value_t tmp;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
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("[uncore,%d] illegal row-index %d", __LINE__, ri));
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tmp = rdmsr(UCF_CTR0 + ri);
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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*v = ucf_perfctr_value_to_reload_count(tmp);
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else
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*v = tmp;
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PMCDBG3(MDP,REA,1, "ucf-read cpu=%d ri=%d -> v=%jx", cpu, ri, *v);
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return (0);
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}
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static int
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ucf_release_pmc(int cpu, int ri, struct pmc *pmc)
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{
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PMCDBG3(MDP,REL,1, "ucf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc);
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
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("[uncore,%d] illegal row-index %d", __LINE__, ri));
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KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri + uncore_ucf_ri].phw_pmc == NULL,
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("[uncore,%d] PHW pmc non-NULL", __LINE__));
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return (0);
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}
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static int
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ucf_start_pmc(int cpu, int ri, struct pmc *pm)
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{
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struct uncore_cpu *ucfc;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
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("[uncore,%d] illegal row-index %d", __LINE__, ri));
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PMCDBG2(MDP,STA,1,"ucf-start cpu=%d ri=%d", cpu, ri);
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ucfc = uncore_pcpu[cpu];
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ucfc->pc_ucfctrl |= pm->pm_md.pm_ucf.pm_ucf_ctrl;
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wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
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ucfc->pc_globalctrl |= (1ULL << (ri + SELECTOFF(uncore_cputype)));
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wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
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PMCDBG4(MDP,STA,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)",
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ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),
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ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL));
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return (0);
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}
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static int
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ucf_stop_pmc(int cpu, int ri, struct pmc *pm __unused)
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{
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uint32_t fc;
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struct uncore_cpu *ucfc;
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PMCDBG2(MDP,STO,1,"ucf-stop cpu=%d ri=%d", cpu, ri);
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ucfc = uncore_pcpu[cpu];
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
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("[uncore,%d] illegal row-index %d", __LINE__, ri));
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fc = (UCF_MASK << (ri * 4));
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ucfc->pc_ucfctrl &= ~fc;
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PMCDBG1(MDP,STO,1,"ucf-stop ucfctrl=%x", ucfc->pc_ucfctrl);
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wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
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/* Don't need to write UC_GLOBAL_CTRL, one disable is enough. */
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PMCDBG4(MDP,STO,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)",
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ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),
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ucfc->pc_globalctrl, rdmsr(UC_GLOBAL_CTRL));
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return (0);
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}
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static int
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ucf_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v)
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{
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struct uncore_cpu *cc;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < uncore_ucf_npmc,
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("[uncore,%d] illegal row-index %d", __LINE__, ri));
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cc = uncore_pcpu[cpu];
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if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
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v = ucf_reload_count_to_perfctr_value(v);
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wrmsr(UCF_CTRL, 0); /* Turn off fixed counters */
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wrmsr(UCF_CTR0 + ri, v);
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wrmsr(UCF_CTRL, cc->pc_ucfctrl);
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PMCDBG4(MDP,WRI,1, "ucf-write cpu=%d ri=%d v=%jx ucfctrl=%jx ",
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cpu, ri, v, (uintmax_t) rdmsr(UCF_CTRL));
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return (0);
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}
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static void
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ucf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
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{
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struct pmc_classdep *pcd;
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KASSERT(md != NULL, ("[ucf,%d] md is NULL", __LINE__));
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PMCDBG0(MDP,INI,1, "ucf-initialize");
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pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCF];
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pcd->pcd_caps = UCF_PMC_CAPS;
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pcd->pcd_class = PMC_CLASS_UCF;
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pcd->pcd_num = npmc;
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pcd->pcd_ri = md->pmd_npmc;
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pcd->pcd_width = pmcwidth;
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pcd->pcd_allocate_pmc = ucf_allocate_pmc;
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pcd->pcd_config_pmc = ucf_config_pmc;
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pcd->pcd_describe = ucf_describe;
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pcd->pcd_get_config = ucf_get_config;
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pcd->pcd_get_msr = NULL;
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pcd->pcd_pcpu_fini = uncore_pcpu_noop;
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pcd->pcd_pcpu_init = uncore_pcpu_noop;
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pcd->pcd_read_pmc = ucf_read_pmc;
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pcd->pcd_release_pmc = ucf_release_pmc;
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pcd->pcd_start_pmc = ucf_start_pmc;
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pcd->pcd_stop_pmc = ucf_stop_pmc;
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pcd->pcd_write_pmc = ucf_write_pmc;
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md->pmd_npmc += npmc;
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}
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/*
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* Intel programmable PMCs.
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*/
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/*
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* Event descriptor tables.
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*
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* For each event id, we track:
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*
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* 1. The CPUs that the event is valid for.
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*
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* 2. If the event uses a fixed UMASK, the value of the umask field.
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* If the event doesn't use a fixed UMASK, a mask of legal bits
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* to check against.
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*/
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struct ucp_event_descr {
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enum pmc_event ucp_ev;
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unsigned char ucp_evcode;
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unsigned char ucp_umask;
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unsigned char ucp_flags;
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};
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#define UCP_F_I7 (1 << 0) /* CPU: Core i7 */
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#define UCP_F_WM (1 << 1) /* CPU: Westmere */
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#define UCP_F_SB (1 << 2) /* CPU: Sandy Bridge */
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#define UCP_F_HW (1 << 3) /* CPU: Haswell */
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#define UCP_F_FM (1 << 4) /* Fixed mask */
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#define UCP_F_ALLCPUS \
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(UCP_F_I7 | UCP_F_WM)
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#define UCP_F_CMASK 0xFF000000
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static pmc_value_t
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ucp_perfctr_value_to_reload_count(pmc_value_t v)
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{
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v &= (1ULL << uncore_ucp_width) - 1;
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return (1ULL << uncore_ucp_width) - v;
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}
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static pmc_value_t
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ucp_reload_count_to_perfctr_value(pmc_value_t rlc)
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{
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return (1ULL << uncore_ucp_width) - rlc;
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}
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/*
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* Counter specific event information for Sandybridge and Haswell
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*/
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static int
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ucp_event_sb_hw_ok_on_counter(uint8_t ev, int ri)
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{
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uint32_t mask;
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switch (ev) {
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/*
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* Events valid only on counter 0.
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*/
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case 0x80:
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case 0x83:
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mask = (1 << 0);
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break;
|
|
|
|
default:
|
|
mask = ~0; /* Any row index is ok. */
|
|
}
|
|
|
|
return (mask & (1 << ri));
|
|
}
|
|
|
|
static int
|
|
ucp_allocate_pmc(int cpu, int ri, struct pmc *pm,
|
|
const struct pmc_op_pmcallocate *a)
|
|
{
|
|
uint8_t ev;
|
|
const struct pmc_md_ucp_op_pmcallocate *ucp;
|
|
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
|
("[uncore,%d] illegal CPU %d", __LINE__, cpu));
|
|
KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
|
|
("[uncore,%d] illegal row-index value %d", __LINE__, ri));
|
|
|
|
if (a->pm_class != PMC_CLASS_UCP)
|
|
return (EINVAL);
|
|
|
|
ucp = &a->pm_md.pm_ucp;
|
|
ev = UCP_EVSEL(ucp->pm_ucp_config);
|
|
switch (uncore_cputype) {
|
|
case PMC_CPU_INTEL_HASWELL:
|
|
case PMC_CPU_INTEL_SANDYBRIDGE:
|
|
if (ucp_event_sb_hw_ok_on_counter(ev, ri) == 0)
|
|
return (EINVAL);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
pm->pm_md.pm_ucp.pm_ucp_evsel = ucp->pm_ucp_config | UCP_EN;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ucp_config_pmc(int cpu, int ri, struct pmc *pm)
|
|
{
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
|
("[uncore,%d] illegal CPU %d", __LINE__, cpu));
|
|
|
|
KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
|
|
("[uncore,%d] illegal row-index %d", __LINE__, ri));
|
|
|
|
PMCDBG3(MDP,CFG,1, "ucp-config cpu=%d ri=%d pm=%p", cpu, ri, pm);
|
|
|
|
KASSERT(uncore_pcpu[cpu] != NULL, ("[uncore,%d] null per-cpu %d", __LINE__,
|
|
cpu));
|
|
|
|
uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc = pm;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ucp_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
|
|
{
|
|
struct pmc_hw *phw;
|
|
|
|
phw = &uncore_pcpu[cpu]->pc_uncorepmcs[ri];
|
|
|
|
snprintf(pi->pm_name, sizeof(pi->pm_name), "UCP-%d", ri);
|
|
pi->pm_class = PMC_CLASS_UCP;
|
|
|
|
if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
|
|
pi->pm_enabled = TRUE;
|
|
*ppmc = phw->phw_pmc;
|
|
} else {
|
|
pi->pm_enabled = FALSE;
|
|
*ppmc = NULL;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ucp_get_config(int cpu, int ri, struct pmc **ppm)
|
|
{
|
|
*ppm = uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ucp_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v)
|
|
{
|
|
pmc_value_t tmp;
|
|
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
|
("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
|
|
KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
|
|
("[uncore,%d] illegal row-index %d", __LINE__, ri));
|
|
|
|
tmp = rdmsr(UCP_PMC0 + ri);
|
|
if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
|
|
*v = ucp_perfctr_value_to_reload_count(tmp);
|
|
else
|
|
*v = tmp;
|
|
|
|
PMCDBG4(MDP,REA,1, "ucp-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri,
|
|
ri, *v);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ucp_release_pmc(int cpu, int ri, struct pmc *pm)
|
|
{
|
|
(void) pm;
|
|
|
|
PMCDBG3(MDP,REL,1, "ucp-release cpu=%d ri=%d pm=%p", cpu, ri,
|
|
pm);
|
|
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
|
("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
|
|
KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
|
|
("[uncore,%d] illegal row-index %d", __LINE__, ri));
|
|
|
|
KASSERT(uncore_pcpu[cpu]->pc_uncorepmcs[ri].phw_pmc
|
|
== NULL, ("[uncore,%d] PHW pmc non-NULL", __LINE__));
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ucp_start_pmc(int cpu, int ri, struct pmc *pm)
|
|
{
|
|
uint64_t evsel;
|
|
struct uncore_cpu *cc;
|
|
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
|
("[uncore,%d] illegal CPU value %d", __LINE__, cpu));
|
|
KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
|
|
("[uncore,%d] illegal row-index %d", __LINE__, ri));
|
|
|
|
cc = uncore_pcpu[cpu];
|
|
|
|
PMCDBG2(MDP,STA,1, "ucp-start cpu=%d ri=%d", cpu, ri);
|
|
|
|
evsel = pm->pm_md.pm_ucp.pm_ucp_evsel;
|
|
|
|
PMCDBG4(MDP,STA,2,
|
|
"ucp-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x",
|
|
cpu, ri, SELECTSEL(uncore_cputype) + ri, evsel);
|
|
|
|
wrmsr(SELECTSEL(uncore_cputype) + ri, evsel);
|
|
|
|
cc->pc_globalctrl |= (1ULL << ri);
|
|
wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ucp_stop_pmc(int cpu, int ri, struct pmc *pm __unused)
|
|
{
|
|
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
|
("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
|
|
KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
|
|
("[uncore,%d] illegal row index %d", __LINE__, ri));
|
|
|
|
PMCDBG2(MDP,STO,1, "ucp-stop cpu=%d ri=%d", cpu, ri);
|
|
|
|
/* stop hw. */
|
|
wrmsr(SELECTSEL(uncore_cputype) + ri, 0);
|
|
|
|
/* Don't need to write UC_GLOBAL_CTRL, one disable is enough. */
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ucp_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v)
|
|
{
|
|
|
|
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
|
("[uncore,%d] illegal cpu value %d", __LINE__, cpu));
|
|
KASSERT(ri >= 0 && ri < uncore_ucp_npmc,
|
|
("[uncore,%d] illegal row index %d", __LINE__, ri));
|
|
|
|
PMCDBG4(MDP,WRI,1, "ucp-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri,
|
|
UCP_PMC0 + ri, v);
|
|
|
|
if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm)))
|
|
v = ucp_reload_count_to_perfctr_value(v);
|
|
|
|
/*
|
|
* Write the new value to the counter. The counter will be in
|
|
* a stopped state when the pcd_write() entry point is called.
|
|
*/
|
|
|
|
wrmsr(UCP_PMC0 + ri, v);
|
|
|
|
return (0);
|
|
}
|
|
|
|
|
|
static void
|
|
ucp_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth)
|
|
{
|
|
struct pmc_classdep *pcd;
|
|
|
|
KASSERT(md != NULL, ("[ucp,%d] md is NULL", __LINE__));
|
|
|
|
PMCDBG0(MDP,INI,1, "ucp-initialize");
|
|
|
|
pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_UCP];
|
|
|
|
pcd->pcd_caps = UCP_PMC_CAPS;
|
|
pcd->pcd_class = PMC_CLASS_UCP;
|
|
pcd->pcd_num = npmc;
|
|
pcd->pcd_ri = md->pmd_npmc;
|
|
pcd->pcd_width = pmcwidth;
|
|
|
|
pcd->pcd_allocate_pmc = ucp_allocate_pmc;
|
|
pcd->pcd_config_pmc = ucp_config_pmc;
|
|
pcd->pcd_describe = ucp_describe;
|
|
pcd->pcd_get_config = ucp_get_config;
|
|
pcd->pcd_get_msr = NULL;
|
|
pcd->pcd_pcpu_fini = uncore_pcpu_fini;
|
|
pcd->pcd_pcpu_init = uncore_pcpu_init;
|
|
pcd->pcd_read_pmc = ucp_read_pmc;
|
|
pcd->pcd_release_pmc = ucp_release_pmc;
|
|
pcd->pcd_start_pmc = ucp_start_pmc;
|
|
pcd->pcd_stop_pmc = ucp_stop_pmc;
|
|
pcd->pcd_write_pmc = ucp_write_pmc;
|
|
|
|
md->pmd_npmc += npmc;
|
|
}
|
|
|
|
int
|
|
pmc_uncore_initialize(struct pmc_mdep *md, int maxcpu)
|
|
{
|
|
uncore_cputype = md->pmd_cputype;
|
|
uncore_pmcmask = 0;
|
|
|
|
/*
|
|
* Initialize programmable counters.
|
|
*/
|
|
|
|
uncore_ucp_npmc = 8;
|
|
uncore_ucp_width = 48;
|
|
|
|
uncore_pmcmask |= ((1ULL << uncore_ucp_npmc) - 1);
|
|
|
|
ucp_initialize(md, maxcpu, uncore_ucp_npmc, uncore_ucp_width);
|
|
|
|
/*
|
|
* Initialize fixed function counters, if present.
|
|
*/
|
|
uncore_ucf_ri = uncore_ucp_npmc;
|
|
uncore_ucf_npmc = 1;
|
|
uncore_ucf_width = 48;
|
|
|
|
ucf_initialize(md, maxcpu, uncore_ucf_npmc, uncore_ucf_width);
|
|
uncore_pmcmask |= ((1ULL << uncore_ucf_npmc) - 1) << SELECTOFF(uncore_cputype);
|
|
|
|
PMCDBG2(MDP,INI,1,"uncore-init pmcmask=0x%jx ucfri=%d", uncore_pmcmask,
|
|
uncore_ucf_ri);
|
|
|
|
uncore_pcpu = malloc(sizeof(*uncore_pcpu) * maxcpu, M_PMC,
|
|
M_ZERO | M_WAITOK);
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
pmc_uncore_finalize(struct pmc_mdep *md)
|
|
{
|
|
PMCDBG0(MDP,INI,1, "uncore-finalize");
|
|
|
|
free(uncore_pcpu, M_PMC);
|
|
uncore_pcpu = NULL;
|
|
}
|