618 lines
16 KiB
C
618 lines
16 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2017 Ian Lepore <ian@freebsd.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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/*
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* Driver for Dallas/Maxim DS13xx real-time clock/calendar chips:
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*
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* - DS1307 = Original/basic rtc + 56 bytes ram; 5v only.
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* - DS1308 = Updated 1307, available in 1.8v-5v variations.
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* - DS1337 = Like 1308, integrated xtal, 32khz output on at powerup.
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* - DS1338 = Like 1308, integrated xtal.
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* - DS1339 = Like 1337, integrated xtal, integrated trickle charger.
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* - DS1340 = Like 1338, ST M41T00 compatible.
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* - DS1341 = Like 1338, can slave-sync osc to external clock signal.
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* - DS1342 = Like 1341 but requires different xtal.
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* - DS1371 = 32-bit binary counter, watchdog timer.
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* - DS1372 = 32-bit binary counter, 64-bit unique id in rom.
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* - DS1374 = 32-bit binary counter, watchdog timer, trickle charger.
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* - DS1375 = Like 1308 but only 16 bytes ram.
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* - DS1388 = Rtc, watchdog timer, 512 bytes eeprom (not sram).
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*
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* This driver supports only basic timekeeping functions. It provides no access
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* to or control over any other functionality provided by the chips.
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*/
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/clock.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/libkern.h>
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#include <sys/module.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/iicbus/iiconf.h>
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#ifdef FDT
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#endif
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#include "clock_if.h"
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#include "iicbus_if.h"
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/*
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* I2C address 1101 000x
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*/
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#define DS13xx_ADDR 0xd0
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/*
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* Registers, bits within them, and masks for the various chip types.
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*/
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#define DS13xx_R_NONE 0xff /* Placeholder */
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#define DS130x_R_CONTROL 0x07
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#define DS133x_R_CONTROL 0x0e
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#define DS1340_R_CONTROL 0x07
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#define DS1341_R_CONTROL 0x0e
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#define DS1371_R_CONTROL 0x07
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#define DS1372_R_CONTROL 0x07
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#define DS1374_R_CONTROL 0x07
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#define DS1375_R_CONTROL 0x0e
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#define DS1388_R_CONTROL 0x0c
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#define DS13xx_R_SECOND 0x00
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#define DS1388_R_SECOND 0x01
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#define DS130x_R_STATUS DS13xx_R_NONE
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#define DS133x_R_STATUS 0x0f
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#define DS1340_R_STATUS 0x09
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#define DS137x_R_STATUS 0x08
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#define DS1388_R_STATUS 0x0b
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#define DS13xx_B_STATUS_OSF 0x80 /* OSF is 1<<7 in status and sec regs */
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#define DS13xx_B_HOUR_AMPM 0x40 /* AMPM mode is bit 1<<6 */
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#define DS13xx_B_HOUR_PM 0x20 /* PM hours indicated by 1<<5 */
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#define DS13xx_B_MONTH_CENTURY 0x80 /* 21st century indicated by 1<<7 */
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#define DS13xx_M_SECOND 0x7f /* Masks for all BCD time regs... */
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#define DS13xx_M_MINUTE 0x7f
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#define DS13xx_M_12HOUR 0x1f
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#define DS13xx_M_24HOUR 0x3f
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#define DS13xx_M_DAY 0x3f
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#define DS13xx_M_MONTH 0x1f
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#define DS13xx_M_YEAR 0xff
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/*
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* The chip types we support.
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*/
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enum {
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TYPE_NONE,
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TYPE_DS1307,
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TYPE_DS1308,
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TYPE_DS1337,
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TYPE_DS1338,
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TYPE_DS1339,
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TYPE_DS1340,
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TYPE_DS1341,
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TYPE_DS1342,
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TYPE_DS1371,
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TYPE_DS1372,
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TYPE_DS1374,
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TYPE_DS1375,
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TYPE_DS1388,
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TYPE_COUNT
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};
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static const char *desc_strings[] = {
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"",
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"Dallas/Maxim DS1307 RTC",
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"Dallas/Maxim DS1308 RTC",
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"Dallas/Maxim DS1337 RTC",
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"Dallas/Maxim DS1338 RTC",
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"Dallas/Maxim DS1339 RTC",
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"Dallas/Maxim DS1340 RTC",
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"Dallas/Maxim DS1341 RTC",
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"Dallas/Maxim DS1342 RTC",
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"Dallas/Maxim DS1371 RTC",
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"Dallas/Maxim DS1372 RTC",
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"Dallas/Maxim DS1374 RTC",
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"Dallas/Maxim DS1375 RTC",
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"Dallas/Maxim DS1388 RTC",
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};
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CTASSERT(nitems(desc_strings) == TYPE_COUNT);
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/*
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* The time registers in the order they are laid out in hardware.
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*/
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struct time_regs {
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uint8_t sec, min, hour, wday, day, month, year;
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};
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struct ds13rtc_softc {
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device_t dev;
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device_t busdev;
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u_int chiptype; /* Type of DS13xx chip */
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uint8_t secaddr; /* Address of seconds register */
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uint8_t osfaddr; /* Address of register with OSF */
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bool use_ampm; /* Use AM/PM mode. */
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bool use_century; /* Use the Century bit. */
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bool is_binary_counter; /* Chip has 32-bit binary counter. */
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};
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/*
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* We use the compat_data table to look up hint strings in the non-FDT case, so
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* define the struct locally when we don't get it from ofw_bus_subr.h.
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*/
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#ifdef FDT
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typedef struct ofw_compat_data ds13_compat_data;
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#else
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typedef struct {
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const char *ocd_str;
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uintptr_t ocd_data;
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} ds13_compat_data;
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#endif
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static ds13_compat_data compat_data[] = {
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{"dallas,ds1307", TYPE_DS1307},
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{"dallas,ds1308", TYPE_DS1308},
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{"dallas,ds1337", TYPE_DS1337},
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{"dallas,ds1338", TYPE_DS1338},
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{"dallas,ds1339", TYPE_DS1339},
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{"dallas,ds1340", TYPE_DS1340},
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{"dallas,ds1341", TYPE_DS1341},
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{"dallas,ds1342", TYPE_DS1342},
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{"dallas,ds1371", TYPE_DS1371},
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{"dallas,ds1372", TYPE_DS1372},
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{"dallas,ds1374", TYPE_DS1374},
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{"dallas,ds1375", TYPE_DS1375},
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{"dallas,ds1388", TYPE_DS1388},
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{NULL, TYPE_NONE},
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};
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static int
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read_reg(struct ds13rtc_softc *sc, uint8_t reg, uint8_t *val)
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{
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return (iicdev_readfrom(sc->dev, reg, val, sizeof(*val), IIC_WAIT));
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}
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static int
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write_reg(struct ds13rtc_softc *sc, uint8_t reg, uint8_t val)
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{
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return (iicdev_writeto(sc->dev, reg, &val, sizeof(val), IIC_WAIT));
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}
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static int
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read_timeregs(struct ds13rtc_softc *sc, struct time_regs *tregs)
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{
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int err;
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if ((err = iicdev_readfrom(sc->dev, sc->secaddr, tregs,
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sizeof(*tregs), IIC_WAIT)) != 0)
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return (err);
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return (err);
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}
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static int
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write_timeregs(struct ds13rtc_softc *sc, struct time_regs *tregs)
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{
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return (iicdev_writeto(sc->dev, sc->secaddr, tregs,
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sizeof(*tregs), IIC_WAIT));
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}
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static int
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read_timeword(struct ds13rtc_softc *sc, time_t *secs)
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{
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int err;
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uint8_t buf[4];
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if ((err = iicdev_readfrom(sc->dev, sc->secaddr, buf, sizeof(buf),
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IIC_WAIT)) == 0)
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*secs = le32dec(buf);
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return (err);
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}
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static int
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write_timeword(struct ds13rtc_softc *sc, time_t secs)
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{
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uint8_t buf[4];
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le32enc(buf, (uint32_t)secs);
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return (iicdev_writeto(sc->dev, sc->secaddr, buf, sizeof(buf),
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IIC_WAIT));
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}
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static void
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ds13rtc_start(void *arg)
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{
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struct ds13rtc_softc *sc;
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uint8_t ctlreg, statreg;
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sc = arg;
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/*
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* Every chip in this family can be usefully initialized by writing 0 to
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* the control register, except DS1375 which has an external oscillator
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* controlled by values in the ctlreg that we know nothing about, so
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* we'd best leave them alone. For all other chips, writing 0 enables
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* the oscillator, disables signals/outputs in battery-backed mode
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* (saves power) and disables features like watchdog timers and alarms.
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*/
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switch (sc->chiptype) {
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case TYPE_DS1307:
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case TYPE_DS1308:
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case TYPE_DS1338:
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case TYPE_DS1340:
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case TYPE_DS1371:
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case TYPE_DS1372:
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case TYPE_DS1374:
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ctlreg = DS130x_R_CONTROL;
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break;
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case TYPE_DS1337:
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case TYPE_DS1339:
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ctlreg = DS133x_R_CONTROL;
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break;
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case TYPE_DS1341:
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case TYPE_DS1342:
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ctlreg = DS1341_R_CONTROL;
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break;
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case TYPE_DS1375:
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ctlreg = DS13xx_R_NONE;
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break;
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case TYPE_DS1388:
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ctlreg = DS1388_R_CONTROL;
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break;
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default:
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device_printf(sc->dev, "missing init code for this chiptype\n");
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return;
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}
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if (ctlreg != DS13xx_R_NONE)
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write_reg(sc, ctlreg, 0);
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/*
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* Common init. Read the OSF/CH status bit and report stopped clocks to
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* the user. The status bit will be cleared the first time we write
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* valid time to the chip (and must not be cleared before that).
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*/
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if (read_reg(sc, sc->osfaddr, &statreg) != 0) {
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device_printf(sc->dev, "cannot read RTC clock status bit\n");
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return;
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}
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if (statreg & DS13xx_B_STATUS_OSF) {
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device_printf(sc->dev,
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"WARNING: RTC battery failed; time is invalid\n");
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}
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/*
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* Figure out whether the chip is configured for AM/PM mode. On all
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* chips that do AM/PM mode, the flag bit is in the hours register,
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* which is secaddr+2.
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*/
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if ((sc->chiptype != TYPE_DS1340) && !sc->is_binary_counter) {
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if (read_reg(sc, sc->secaddr + 2, &statreg) != 0) {
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device_printf(sc->dev,
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"cannot read RTC clock AM/PM bit\n");
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return;
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}
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if (statreg & DS13xx_B_HOUR_AMPM)
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sc->use_ampm = true;
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}
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/*
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* Everything looks good if we make it to here; register as an RTC.
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* Schedule RTC updates to happen just after top-of-second.
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*/
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clock_register_flags(sc->dev, 1000000, CLOCKF_SETTIME_NO_ADJ);
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clock_schedule(sc->dev, 1);
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}
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static int
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ds13rtc_gettime(device_t dev, struct timespec *ts)
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{
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struct bcd_clocktime bct;
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struct time_regs tregs;
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struct ds13rtc_softc *sc;
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int err;
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uint8_t statreg, hourmask;
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sc = device_get_softc(dev);
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/* Read the OSF/CH bit; if the clock stopped we can't provide time. */
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if ((err = read_reg(sc, sc->osfaddr, &statreg)) != 0) {
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return (err);
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}
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if (statreg & DS13xx_B_STATUS_OSF)
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return (EINVAL); /* hardware is good, time is not. */
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/* If the chip counts time in binary, we just read and return it. */
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if (sc->is_binary_counter) {
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ts->tv_nsec = 0;
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return (read_timeword(sc, &ts->tv_sec));
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}
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/*
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* Chip counts in BCD, read and decode it...
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*/
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if ((err = read_timeregs(sc, &tregs)) != 0) {
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device_printf(dev, "cannot read RTC time\n");
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return (err);
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}
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if (sc->use_ampm)
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hourmask = DS13xx_M_12HOUR;
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else
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hourmask = DS13xx_M_24HOUR;
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bct.nsec = 0;
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bct.ispm = tregs.hour & DS13xx_B_HOUR_PM;
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bct.sec = tregs.sec & DS13xx_M_SECOND;
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bct.min = tregs.min & DS13xx_M_MINUTE;
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bct.hour = tregs.hour & hourmask;
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bct.day = tregs.day & DS13xx_M_DAY;
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bct.mon = tregs.month & DS13xx_M_MONTH;
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bct.year = tregs.year & DS13xx_M_YEAR;
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/*
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* If this chip has a century bit, honor it. Otherwise let
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* clock_ct_to_ts() infer the century from the 2-digit year.
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*/
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if (sc->use_century)
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bct.year += (tregs.month & DS13xx_B_MONTH_CENTURY) ? 0x100 : 0;
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clock_dbgprint_bcd(sc->dev, CLOCK_DBG_READ, &bct);
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err = clock_bcd_to_ts(&bct, ts, sc->use_ampm);
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return (err);
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}
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static int
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ds13rtc_settime(device_t dev, struct timespec *ts)
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{
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struct bcd_clocktime bct;
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struct time_regs tregs;
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struct ds13rtc_softc *sc;
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int err;
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uint8_t cflag, statreg, pmflags;
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sc = device_get_softc(dev);
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/*
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* We request a timespec with no resolution-adjustment. That also
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* disables utc adjustment, so apply that ourselves.
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*/
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ts->tv_sec -= utc_offset();
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/* If the chip counts time in binary, store tv_sec and we're done. */
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if (sc->is_binary_counter)
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return (write_timeword(sc, ts->tv_sec));
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clock_ts_to_bcd(ts, &bct, sc->use_ampm);
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clock_dbgprint_bcd(sc->dev, CLOCK_DBG_WRITE, &bct);
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/* If the chip is in AMPM mode deal with the PM flag. */
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pmflags = 0;
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if (sc->use_ampm) {
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pmflags = DS13xx_B_HOUR_AMPM;
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if (bct.ispm)
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pmflags |= DS13xx_B_HOUR_PM;
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}
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/* If the chip has a century bit, set it as needed. */
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cflag = 0;
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if (sc->use_century) {
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if (bct.year >= 2000)
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cflag |= DS13xx_B_MONTH_CENTURY;
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}
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tregs.sec = bct.sec;
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tregs.min = bct.min;
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tregs.hour = bct.hour | pmflags;
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tregs.day = bct.day;
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tregs.month = bct.mon | cflag;
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tregs.year = bct.year & 0xff;
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tregs.wday = bct.dow;
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/*
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* Set the time. Reset the OSF bit if it is on and it is not part of
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* the time registers (in which case writing time resets it).
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*/
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if ((err = write_timeregs(sc, &tregs)) != 0)
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goto errout;
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if (sc->osfaddr != sc->secaddr) {
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if ((err = read_reg(sc, sc->osfaddr, &statreg)) != 0)
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goto errout;
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if (statreg & DS13xx_B_STATUS_OSF) {
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statreg &= ~DS13xx_B_STATUS_OSF;
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err = write_reg(sc, sc->osfaddr, statreg);
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}
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}
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errout:
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if (err != 0)
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device_printf(dev, "cannot update RTC time\n");
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return (err);
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}
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static int
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ds13rtc_get_chiptype(device_t dev)
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{
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#ifdef FDT
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return (ofw_bus_search_compatible(dev, compat_data)->ocd_data);
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#else
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ds13_compat_data *cdata;
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const char *htype;
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/*
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* We can only attach if provided a chiptype hint string.
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*/
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if (resource_string_value(device_get_name(dev),
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device_get_unit(dev), "compatible", &htype) != 0)
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return (TYPE_NONE);
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/*
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* Loop through the ofw compat data comparing the hinted chip type to
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* the compat strings.
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*/
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for (cdata = compat_data; cdata->ocd_str != NULL; ++cdata) {
|
|
if (strcmp(htype, cdata->ocd_str) == 0)
|
|
break;
|
|
}
|
|
return (cdata->ocd_data);
|
|
#endif
|
|
}
|
|
|
|
static int
|
|
ds13rtc_probe(device_t dev)
|
|
{
|
|
int chiptype, goodrv;
|
|
|
|
#ifdef FDT
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
goodrv = BUS_PROBE_GENERIC;
|
|
#else
|
|
goodrv = BUS_PROBE_NOWILDCARD;
|
|
#endif
|
|
|
|
chiptype = ds13rtc_get_chiptype(dev);
|
|
if (chiptype == TYPE_NONE)
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, desc_strings[chiptype]);
|
|
return (goodrv);
|
|
}
|
|
|
|
static int
|
|
ds13rtc_attach(device_t dev)
|
|
{
|
|
struct ds13rtc_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
sc->busdev = device_get_parent(dev);
|
|
|
|
/*
|
|
* We need to know what kind of chip we're driving.
|
|
*/
|
|
if ((sc->chiptype = ds13rtc_get_chiptype(dev)) == TYPE_NONE) {
|
|
device_printf(dev, "impossible: cannot determine chip type\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* The seconds register is in the same place on all except DS1388. */
|
|
if (sc->chiptype == TYPE_DS1388)
|
|
sc->secaddr = DS1388_R_SECOND;
|
|
else
|
|
sc->secaddr = DS13xx_R_SECOND;
|
|
|
|
/*
|
|
* The OSF/CH (osc failed/clock-halted) bit appears in different
|
|
* registers for different chip types. The DS1375 has no OSF indicator
|
|
* because it has no internal oscillator; we just point to an always-
|
|
* zero bit in the status register for that chip.
|
|
*/
|
|
switch (sc->chiptype) {
|
|
case TYPE_DS1307:
|
|
case TYPE_DS1308:
|
|
case TYPE_DS1338:
|
|
sc->osfaddr = DS13xx_R_SECOND;
|
|
break;
|
|
case TYPE_DS1337:
|
|
case TYPE_DS1339:
|
|
case TYPE_DS1341:
|
|
case TYPE_DS1342:
|
|
case TYPE_DS1375:
|
|
sc->osfaddr = DS133x_R_STATUS;
|
|
sc->use_century = true;
|
|
break;
|
|
case TYPE_DS1340:
|
|
sc->osfaddr = DS1340_R_STATUS;
|
|
break;
|
|
case TYPE_DS1371:
|
|
case TYPE_DS1372:
|
|
case TYPE_DS1374:
|
|
sc->osfaddr = DS137x_R_STATUS;
|
|
sc->is_binary_counter = true;
|
|
break;
|
|
case TYPE_DS1388:
|
|
sc->osfaddr = DS1388_R_STATUS;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* We have to wait until interrupts are enabled. Sometimes I2C read
|
|
* and write only works when the interrupts are available.
|
|
*/
|
|
config_intrhook_oneshot(ds13rtc_start, sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ds13rtc_detach(device_t dev)
|
|
{
|
|
|
|
clock_unregister(dev);
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t ds13rtc_methods[] = {
|
|
DEVMETHOD(device_probe, ds13rtc_probe),
|
|
DEVMETHOD(device_attach, ds13rtc_attach),
|
|
DEVMETHOD(device_detach, ds13rtc_detach),
|
|
|
|
DEVMETHOD(clock_gettime, ds13rtc_gettime),
|
|
DEVMETHOD(clock_settime, ds13rtc_settime),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t ds13rtc_driver = {
|
|
"ds13rtc",
|
|
ds13rtc_methods,
|
|
sizeof(struct ds13rtc_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(ds13rtc, iicbus, ds13rtc_driver, NULL, NULL);
|
|
MODULE_VERSION(ds13rtc, 1);
|
|
MODULE_DEPEND(ds13rtc, iicbus, IICBB_MINVER, IICBB_PREFVER, IICBB_MAXVER);
|
|
IICBUS_FDT_PNP_INFO(compat_data);
|