Required for Apple and Microsoft -compatible HID-over-SPI drivers.
Most logic was already implemented in commit 3c08673438
"spibus: extend API: add cs_delay ivar, KEEP_CS and NO_SLEEP flags".
It dissallowed driver sleeps in the interrupt context. This commit
extends this feature to handle ddb/kdb context with following:
- Skip driver locking if SPI functions were called from kdb/ddb.
- Reinitialize controller if kdb/ddb initiated SPI transfer has
interrupted another already running one. Does not work very
reliable yet.
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D41247
618 lines
15 KiB
C
618 lines
15 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2016 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_acpi.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kdb.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include <dev/intel/spi.h>
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/**
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* Macros for driver mutex locking
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*/
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#define INTELSPI_IN_POLLING_MODE() (SCHEDULER_STOPPED() || kdb_active)
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#define INTELSPI_LOCK(_sc) do { \
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if(!INTELSPI_IN_POLLING_MODE()) \
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mtx_lock(&(_sc)->sc_mtx); \
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} while (0)
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#define INTELSPI_UNLOCK(_sc) do { \
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if(!INTELSPI_IN_POLLING_MODE()) \
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mtx_unlock(&(_sc)->sc_mtx); \
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} while (0)
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#define INTELSPI_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
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"intelspi", MTX_DEF)
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#define INTELSPI_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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#define INTELSPI_ASSERT_LOCKED(_sc) do { \
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if(!INTELSPI_IN_POLLING_MODE()) \
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mtx_assert(&(_sc)->sc_mtx, MA_OWNED); \
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} while (0)
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#define INTELSPI_ASSERT_UNLOCKED(_sc) do { \
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if(!INTELSPI_IN_POLLING_MODE()) \
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mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED);\
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} while (0)
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#define INTELSPI_WRITE(_sc, _off, _val) \
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bus_write_4((_sc)->sc_mem_res, (_off), (_val))
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#define INTELSPI_READ(_sc, _off) \
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bus_read_4((_sc)->sc_mem_res, (_off))
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#define INTELSPI_BUSY 0x1
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#define TX_FIFO_THRESHOLD 2
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#define RX_FIFO_THRESHOLD 2
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#define CLOCK_DIV_10MHZ 5
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#define DATA_SIZE_8BITS 8
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#define MAX_CLOCK_RATE 50000000
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#define CS_LOW 0
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#define CS_HIGH 1
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#define INTELSPI_SSPREG_SSCR0 0x0
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#define SSCR0_SCR(n) ((((n) - 1) & 0xfff) << 8)
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#define SSCR0_SSE (1 << 7)
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#define SSCR0_FRF_SPI (0 << 4)
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#define SSCR0_DSS(n) (((n) - 1) << 0)
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#define INTELSPI_SSPREG_SSCR1 0x4
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#define SSCR1_TINTE (1 << 19)
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#define SSCR1_RFT(n) (((n) - 1) << 10)
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#define SSCR1_RFT_MASK (0xf << 10)
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#define SSCR1_TFT(n) (((n) - 1) << 6)
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#define SSCR1_SPI_SPH (1 << 4)
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#define SSCR1_SPI_SPO (1 << 3)
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#define SSCR1_MODE_MASK (SSCR1_SPI_SPO | SSCR1_SPI_SPH)
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#define SSCR1_TIE (1 << 1)
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#define SSCR1_RIE (1 << 0)
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#define INTELSPI_SSPREG_SSSR 0x8
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#define SSSR_RFL_MASK (0xf << 12)
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#define SSSR_TFL_MASK (0xf << 8)
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#define SSSR_RNE (1 << 3)
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#define SSSR_TNF (1 << 2)
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#define INTELSPI_SSPREG_SSITR 0xC
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#define INTELSPI_SSPREG_SSDR 0x10
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#define INTELSPI_SSPREG_SSTO 0x28
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#define INTELSPI_SSPREG_SSPSP 0x2C
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#define INTELSPI_SSPREG_SSTSA 0x30
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#define INTELSPI_SSPREG_SSRSA 0x34
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#define INTELSPI_SSPREG_SSTSS 0x38
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#define INTELSPI_SSPREG_SSACD 0x3C
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#define INTELSPI_SSPREG_ITF 0x40
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#define INTELSPI_SSPREG_SITF 0x44
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#define INTELSPI_SSPREG_SIRF 0x48
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#define SPI_CS_CTRL(sc) \
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(intelspi_infos[sc->sc_vers].reg_lpss_base + \
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intelspi_infos[sc->sc_vers].reg_cs_ctrl)
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#define SPI_CS_CTRL_CS_MASK (3)
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#define SPI_CS_CTRL_SW_MODE (1 << 0)
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#define SPI_CS_CTRL_HW_MODE (1 << 0)
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#define SPI_CS_CTRL_CS_HIGH (1 << 1)
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#define INTELSPI_RESETS 0x204
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#define INTELSPI_RESET_HOST (1 << 0) | (1 << 1)
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#define INTELSPI_RESET_DMA (1 << 2)
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/* Same order as intelspi_vers */
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static const struct intelspi_info {
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uint32_t reg_lpss_base;
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uint32_t reg_cs_ctrl;
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} intelspi_infos[] = {
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[SPI_BAYTRAIL] = {
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.reg_lpss_base = 0x400,
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.reg_cs_ctrl = 0x18,
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},
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[SPI_BRASWELL] = {
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.reg_lpss_base = 0x400,
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.reg_cs_ctrl = 0x18,
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},
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[SPI_LYNXPOINT] = {
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.reg_lpss_base = 0x800,
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.reg_cs_ctrl = 0x18,
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},
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[SPI_SUNRISEPOINT] = {
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.reg_lpss_base = 0x200,
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.reg_cs_ctrl = 0x24,
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},
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};
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static void intelspi_intr(void *);
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static int
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intelspi_txfifo_full(struct intelspi_softc *sc)
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{
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uint32_t sssr;
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INTELSPI_ASSERT_LOCKED(sc);
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sssr = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR);
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if (sssr & SSSR_TNF)
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return (0);
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return (1);
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}
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static int
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intelspi_rxfifo_empty(struct intelspi_softc *sc)
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{
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uint32_t sssr;
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INTELSPI_ASSERT_LOCKED(sc);
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sssr = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR);
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if (sssr & SSSR_RNE)
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return (0);
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else
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return (1);
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}
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static void
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intelspi_fill_tx_fifo(struct intelspi_softc *sc)
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{
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struct spi_command *cmd;
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uint32_t written;
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uint8_t *data;
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INTELSPI_ASSERT_LOCKED(sc);
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cmd = sc->sc_cmd;
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while (sc->sc_written < sc->sc_len &&
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!intelspi_txfifo_full(sc)) {
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data = (uint8_t *)cmd->tx_cmd;
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written = sc->sc_written++;
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if (written >= cmd->tx_cmd_sz) {
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data = (uint8_t *)cmd->tx_data;
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written -= cmd->tx_cmd_sz;
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}
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INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSDR, data[written]);
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}
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}
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static void
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intelspi_drain_rx_fifo(struct intelspi_softc *sc)
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{
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struct spi_command *cmd;
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uint32_t read;
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uint8_t *data;
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INTELSPI_ASSERT_LOCKED(sc);
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cmd = sc->sc_cmd;
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while (sc->sc_read < sc->sc_len &&
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!intelspi_rxfifo_empty(sc)) {
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data = (uint8_t *)cmd->rx_cmd;
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read = sc->sc_read++;
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if (read >= cmd->rx_cmd_sz) {
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data = (uint8_t *)cmd->rx_data;
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read -= cmd->rx_cmd_sz;
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}
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data[read] = INTELSPI_READ(sc, INTELSPI_SSPREG_SSDR) & 0xff;
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}
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}
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static int
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intelspi_transaction_done(struct intelspi_softc *sc)
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{
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int txfifo_empty;
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uint32_t sssr;
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INTELSPI_ASSERT_LOCKED(sc);
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if (sc->sc_written != sc->sc_len ||
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sc->sc_read != sc->sc_len)
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return (0);
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sssr = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR);
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txfifo_empty = ((sssr & SSSR_TFL_MASK) == 0) &&
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(sssr & SSSR_TNF);
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if (txfifo_empty && !(sssr & SSSR_RNE))
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return (1);
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return (0);
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}
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static int
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intelspi_transact(struct intelspi_softc *sc)
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{
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INTELSPI_ASSERT_LOCKED(sc);
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/* TX - Fill up the FIFO. */
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intelspi_fill_tx_fifo(sc);
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/* RX - Drain the FIFO. */
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intelspi_drain_rx_fifo(sc);
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/* Check for end of transfer. */
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return intelspi_transaction_done(sc);
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}
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static void
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intelspi_intr(void *arg)
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{
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struct intelspi_softc *sc;
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uint32_t reg;
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sc = (struct intelspi_softc *)arg;
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INTELSPI_LOCK(sc);
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if ((sc->sc_flags & INTELSPI_BUSY) == 0) {
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INTELSPI_UNLOCK(sc);
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return;
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}
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/* Check if SSP if off */
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reg = INTELSPI_READ(sc, INTELSPI_SSPREG_SSSR);
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if (reg == 0xffffffffU) {
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INTELSPI_UNLOCK(sc);
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return;
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}
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/* Check for end of transfer. */
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if (intelspi_transact(sc)) {
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/* Disable interrupts */
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reg = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1);
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reg &= ~(SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE);
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INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, reg);
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wakeup(sc->sc_dev);
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}
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INTELSPI_UNLOCK(sc);
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}
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static void
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intelspi_init(struct intelspi_softc *sc)
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{
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uint32_t reg;
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INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, 0);
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/* Manual CS control */
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reg = INTELSPI_READ(sc, SPI_CS_CTRL(sc));
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reg &= ~(SPI_CS_CTRL_CS_MASK);
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reg |= (SPI_CS_CTRL_SW_MODE | SPI_CS_CTRL_CS_HIGH);
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INTELSPI_WRITE(sc, SPI_CS_CTRL(sc), reg);
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/* Set TX/RX FIFO IRQ threshold levels */
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reg = SSCR1_TFT(TX_FIFO_THRESHOLD) | SSCR1_RFT(RX_FIFO_THRESHOLD);
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INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, reg);
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reg = SSCR0_SCR(CLOCK_DIV_10MHZ);
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/* Put SSP in SPI mode */
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reg |= SSCR0_FRF_SPI;
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/* Data size */
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reg |= SSCR0_DSS(DATA_SIZE_8BITS);
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/* Enable SSP */
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reg |= SSCR0_SSE;
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INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, reg);
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}
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static void
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intelspi_set_cs(struct intelspi_softc *sc, int level)
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{
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uint32_t reg;
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reg = INTELSPI_READ(sc, SPI_CS_CTRL(sc));
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reg &= ~(SPI_CS_CTRL_CS_MASK);
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reg |= SPI_CS_CTRL_SW_MODE;
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if (level == CS_HIGH)
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reg |= SPI_CS_CTRL_CS_HIGH;
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INTELSPI_WRITE(sc, SPI_CS_CTRL(sc), reg);
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}
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int
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intelspi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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struct intelspi_softc *sc;
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int err, poll_limit;
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uint32_t sscr0, sscr1, mode, clock, cs_delay;
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bool restart = false;
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sc = device_get_softc(dev);
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err = 0;
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KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
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("TX/RX command sizes should be equal"));
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KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
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("TX/RX data sizes should be equal"));
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INTELSPI_LOCK(sc);
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if (!INTELSPI_IN_POLLING_MODE()) {
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/* If the controller is in use wait until it is available. */
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while (sc->sc_flags & INTELSPI_BUSY) {
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if ((cmd->flags & SPI_FLAG_NO_SLEEP) != 0) {
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INTELSPI_UNLOCK(sc);
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return (EBUSY);
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}
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err = mtx_sleep(dev, &sc->sc_mtx, 0, "intelspi", 0);
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if (err == EINTR) {
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INTELSPI_UNLOCK(sc);
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return (err);
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}
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}
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} else {
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/*
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* Now we are in the middle of other transfer. Try to reset
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* controller state to get predictable context.
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*/
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if ((sc->sc_flags & INTELSPI_BUSY) != 0)
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intelspi_init(sc);
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}
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/* Now we have control over SPI controller. */
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sc->sc_flags = INTELSPI_BUSY;
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/* Configure the clock rate and SPI mode. */
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spibus_get_clock(child, &clock);
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spibus_get_mode(child, &mode);
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if (clock != sc->sc_clock || mode != sc->sc_mode) {
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sscr0 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR0);
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sscr0 &= ~SSCR0_SSE;
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INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, sscr0);
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restart = true;
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}
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if (clock != sc->sc_clock) {
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sscr0 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR0);
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sscr0 &= ~SSCR0_SCR(0xfff);
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if (clock == 0)
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sscr0 |= SSCR0_SCR(CLOCK_DIV_10MHZ);
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else
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sscr0 |= SSCR0_SCR(howmany(MAX_CLOCK_RATE, min(MAX_CLOCK_RATE, clock)));
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INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, sscr0);
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sc->sc_clock = clock;
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}
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if (mode != sc->sc_mode) {
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sscr1 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1);
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sscr1 &= ~SSCR1_MODE_MASK;
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if (mode & SPIBUS_MODE_CPHA)
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sscr1 |= SSCR1_SPI_SPH;
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if (mode & SPIBUS_MODE_CPOL)
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sscr1 |= SSCR1_SPI_SPO;
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INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, sscr1);
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sc->sc_mode = mode;
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}
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if (restart) {
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sscr0 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR0);
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sscr0 |= SSCR0_SSE;
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INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, sscr0);
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}
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/* Save a pointer to the SPI command. */
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sc->sc_cmd = cmd;
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sc->sc_read = 0;
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sc->sc_written = 0;
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sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
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/* Enable CS */
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intelspi_set_cs(sc, CS_LOW);
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/* Wait the CS delay */
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spibus_get_cs_delay(child, &cs_delay);
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DELAY(cs_delay);
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/* Transfer as much as possible to FIFOs */
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if ((cmd->flags & SPI_FLAG_NO_SLEEP) != 0 ||
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INTELSPI_IN_POLLING_MODE() || cold) {
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/* We cannot wait with mtx_sleep if we're called from e.g. an ithread */
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poll_limit = 2000;
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while (!intelspi_transact(sc) && poll_limit-- > 0)
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DELAY(1000);
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if (poll_limit == 0) {
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device_printf(dev, "polling was stuck, transaction not finished\n");
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err = EIO;
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}
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} else {
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if (!intelspi_transact(sc)) {
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/* If FIFO is not large enough - enable interrupts */
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sscr1 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1);
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sscr1 |= (SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE);
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INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, sscr1);
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/* and wait for transaction to complete */
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err = mtx_sleep(dev, &sc->sc_mtx, 0, "intelspi", hz * 2);
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}
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}
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/* De-assert CS */
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if ((cmd->flags & SPI_FLAG_KEEP_CS) == 0)
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intelspi_set_cs(sc, CS_HIGH);
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/* Clear transaction details */
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sc->sc_cmd = NULL;
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sc->sc_read = 0;
|
|
sc->sc_written = 0;
|
|
sc->sc_len = 0;
|
|
|
|
/* Make sure the SPI engine and interrupts are disabled. */
|
|
sscr1 = INTELSPI_READ(sc, INTELSPI_SSPREG_SSCR1);
|
|
sscr1 &= ~(SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE);
|
|
INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR1, sscr1);
|
|
|
|
/* Release the controller and wakeup the next thread waiting for it. */
|
|
sc->sc_flags = 0;
|
|
if (!INTELSPI_IN_POLLING_MODE())
|
|
wakeup_one(dev);
|
|
INTELSPI_UNLOCK(sc);
|
|
|
|
/*
|
|
* Check for transfer timeout. The SPI controller doesn't
|
|
* return errors.
|
|
*/
|
|
if (err == EWOULDBLOCK) {
|
|
device_printf(sc->sc_dev, "transfer timeout\n");
|
|
err = EIO;
|
|
}
|
|
|
|
return (err);
|
|
}
|
|
|
|
int
|
|
intelspi_attach(device_t dev)
|
|
{
|
|
struct intelspi_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->sc_dev = dev;
|
|
|
|
INTELSPI_LOCK_INIT(sc);
|
|
|
|
sc->sc_mem_res = bus_alloc_resource_any(sc->sc_dev,
|
|
SYS_RES_MEMORY, &sc->sc_mem_rid, RF_ACTIVE);
|
|
if (sc->sc_mem_res == NULL) {
|
|
device_printf(dev, "can't allocate memory resource\n");
|
|
goto error;
|
|
}
|
|
|
|
/* Release LPSS reset */
|
|
if (sc->sc_vers == SPI_SUNRISEPOINT)
|
|
INTELSPI_WRITE(sc, INTELSPI_RESETS,
|
|
(INTELSPI_RESET_HOST | INTELSPI_RESET_DMA));
|
|
|
|
sc->sc_irq_res = bus_alloc_resource_any(sc->sc_dev,
|
|
SYS_RES_IRQ, &sc->sc_irq_rid, RF_ACTIVE | RF_SHAREABLE);
|
|
if (sc->sc_irq_res == NULL) {
|
|
device_printf(dev, "can't allocate IRQ resource\n");
|
|
goto error;
|
|
}
|
|
|
|
/* Hook up our interrupt handler. */
|
|
if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
|
|
NULL, intelspi_intr, sc, &sc->sc_irq_ih)) {
|
|
device_printf(dev, "cannot setup the interrupt handler\n");
|
|
goto error;
|
|
}
|
|
|
|
intelspi_init(sc);
|
|
|
|
device_add_child(dev, "spibus", -1);
|
|
|
|
return (bus_delayed_attach_children(dev));
|
|
|
|
error:
|
|
INTELSPI_LOCK_DESTROY(sc);
|
|
|
|
if (sc->sc_mem_res != NULL)
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
sc->sc_mem_rid, sc->sc_mem_res);
|
|
|
|
if (sc->sc_irq_res != NULL)
|
|
bus_release_resource(dev, SYS_RES_IRQ,
|
|
sc->sc_irq_rid, sc->sc_irq_res);
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
int
|
|
intelspi_detach(device_t dev)
|
|
{
|
|
struct intelspi_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
INTELSPI_LOCK_DESTROY(sc);
|
|
|
|
if (sc->sc_irq_ih)
|
|
bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_ih);
|
|
|
|
if (sc->sc_mem_res != NULL)
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
sc->sc_mem_rid, sc->sc_mem_res);
|
|
|
|
if (sc->sc_irq_res != NULL)
|
|
bus_release_resource(dev, SYS_RES_IRQ,
|
|
sc->sc_irq_rid, sc->sc_irq_res);
|
|
|
|
return (device_delete_children(dev));
|
|
}
|
|
|
|
int
|
|
intelspi_suspend(device_t dev)
|
|
{
|
|
struct intelspi_softc *sc;
|
|
int err, i;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
err = bus_generic_suspend(dev);
|
|
if (err)
|
|
return (err);
|
|
|
|
for (i = 0; i < 9; i++) {
|
|
unsigned long offset = i * sizeof(uint32_t);
|
|
sc->sc_regs[i] = INTELSPI_READ(sc,
|
|
intelspi_infos[sc->sc_vers].reg_lpss_base + offset);
|
|
}
|
|
|
|
/* Shutdown just in case */
|
|
INTELSPI_WRITE(sc, INTELSPI_SSPREG_SSCR0, 0);
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
intelspi_resume(device_t dev)
|
|
{
|
|
struct intelspi_softc *sc;
|
|
int i;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
for (i = 0; i < 9; i++) {
|
|
unsigned long offset = i * sizeof(uint32_t);
|
|
INTELSPI_WRITE(sc,
|
|
intelspi_infos[sc->sc_vers].reg_lpss_base + offset,
|
|
sc->sc_regs[i]);
|
|
}
|
|
|
|
intelspi_init(sc);
|
|
|
|
/* Ensure the next transfer would reconfigure these */
|
|
sc->sc_clock = 0;
|
|
sc->sc_mode = 0;
|
|
|
|
return (bus_generic_resume(dev));
|
|
}
|