347 lines
12 KiB
C
347 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2009-2020 Alexander Motin <mav@FreeBSD.org>
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* Copyright (c) 1997-2009 by Matthew Jacob
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Machine Independent (well, as best as possible) register
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* definitions for Qlogic ISP SCSI adapters.
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*/
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#ifndef _ISPREG_H
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#define _ISPREG_H
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/*
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* Hardware definitions for the Qlogic ISP registers.
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*/
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/*
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* This defines types of access to various registers.
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*
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* R: Read Only
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* W: Write Only
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* RW: Read/Write
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*
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* R*, W*, RW*: Read Only, Write Only, Read/Write, but only
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* if RISC processor in ISP is paused.
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*/
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/*
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* NB: The *_BLOCK definitions have no specific hardware meaning.
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* They serve simply to note to the MD layer which block of
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* registers offsets are being accessed.
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*/
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#define _NREG_BLKS 2
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#define _BLK_REG_SHFT 7
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#define _BLK_REG_MASK (1 << _BLK_REG_SHFT)
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#define BIU_BLOCK (0 << _BLK_REG_SHFT)
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#define MBOX_BLOCK (1 << _BLK_REG_SHFT)
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#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */
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#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */
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#define BIU_R2HST_ISTAT_MASK 0xff /* intr information && status */
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#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
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#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
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#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */
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#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
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#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */
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#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
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#define ISPR2HST_RSPQ_UPDATE2 0x14 /* Response Queue Update */
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#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */
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#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */
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#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */
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#define ISPR2HST_ATIO_UPDATE 0x1C /* ATIO Queue Update */
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#define ISPR2HST_ATIO_RSPQ_UPDATE 0x1D /* ATIO & Request Update */
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#define ISPR2HST_ATIO_UPDATE2 0x1E /* ATIO Queue Update */
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/*
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* 2400 Interface Offsets and Register Definitions
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*
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* The 2400 looks quite different in terms of registers from other QLogic cards.
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* It is getting to be a genuine pain and challenge to keep the same model
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* for all.
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*/
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#define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00) /* Flash Access Address */
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#define BIU2400_FLASH_DATA (BIU_BLOCK+0x04) /* Flash Data */
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#define BIU2400_CSR (BIU_BLOCK+0x08) /* ISP Control/Status */
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#define BIU2400_ICR (BIU_BLOCK+0x0C) /* ISP to PCI Interrupt Control */
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#define BIU2400_ISR (BIU_BLOCK+0x10) /* ISP to PCI Interrupt Status */
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#define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */
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#define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */
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#define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */
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#define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */
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#define BIU2400_PRI_REQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */
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#define BIU2400_PRI_REQOUTP (BIU_BLOCK+0x30) /* Priority Request Q Out */
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#define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */
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#define BIU2400_ATIO_RSPOUTP (BIU_BLOCK+0x40) /* ATIO Queue Out */
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#define BIU2400_R2HSTS (BIU_BLOCK+0x44) /* RISC to Host Status */
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#define BIU2400_HCCR (BIU_BLOCK+0x48) /* Host Command and Control Status */
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#define BIU2400_GPIOD (BIU_BLOCK+0x4C) /* General Purpose I/O Data */
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#define BIU2400_GPIOE (BIU_BLOCK+0x50) /* General Purpose I/O Enable */
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#define BIU2400_IOBBA (BIU_BLOCK+0x54) /* I/O Bus Base Address */
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#define BIU2400_HSEMA (BIU_BLOCK+0x58) /* Host-to-Host Semaphore */
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/* BIU2400_FLASH_ADDR definitions */
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#define BIU2400_FLASH_DFLAG (1 << 30)
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/* BIU2400_CSR definitions */
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#define BIU2400_NVERR (1 << 18)
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#define BIU2400_DMA_ACTIVE (1 << 17) /* RO */
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#define BIU2400_DMA_STOP (1 << 16)
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#define BIU2400_FUNCTION (1 << 15) /* RO */
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#define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */
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#define BIU2400_CSR_64BIT (1 << 2) /* RO */
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#define BIU2400_FLASH_ENABLE (1 << 1)
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#define BIU2400_SOFT_RESET (1 << 0)
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/* BIU2400_ICR definitions */
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#define BIU2400_ICR_ENA_RISC_INT 0x8
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#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT)
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/* BIU2400_ISR definitions */
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#define BIU2400_ISR_RISC_INT 0x8
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/* BIU2400_HCCR definitions */
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#define HCCR_2400_CMD_NOP 0x00000000
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#define HCCR_2400_CMD_RESET 0x10000000
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#define HCCR_2400_CMD_CLEAR_RESET 0x20000000
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#define HCCR_2400_CMD_PAUSE 0x30000000
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#define HCCR_2400_CMD_RELEASE 0x40000000
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#define HCCR_2400_CMD_SET_HOST_INT 0x50000000
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#define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000
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#define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000
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#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */
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#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */
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#define HCCR_2400_RISC_RESET (1 << 5) /* RO */
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/*
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* Mailbox Block Register Offsets
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*/
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#define INMAILBOX0 (MBOX_BLOCK+0x0)
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#define INMAILBOX1 (MBOX_BLOCK+0x2)
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#define INMAILBOX2 (MBOX_BLOCK+0x4)
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#define INMAILBOX3 (MBOX_BLOCK+0x6)
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#define INMAILBOX4 (MBOX_BLOCK+0x8)
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#define INMAILBOX5 (MBOX_BLOCK+0xA)
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#define INMAILBOX6 (MBOX_BLOCK+0xC)
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#define INMAILBOX7 (MBOX_BLOCK+0xE)
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#define OUTMAILBOX0 (MBOX_BLOCK+0x0)
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#define OUTMAILBOX1 (MBOX_BLOCK+0x2)
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#define OUTMAILBOX2 (MBOX_BLOCK+0x4)
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#define OUTMAILBOX3 (MBOX_BLOCK+0x6)
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#define OUTMAILBOX4 (MBOX_BLOCK+0x8)
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#define OUTMAILBOX5 (MBOX_BLOCK+0xA)
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#define OUTMAILBOX6 (MBOX_BLOCK+0xC)
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#define OUTMAILBOX7 (MBOX_BLOCK+0xE)
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#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1))
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#define ISP_NMBOX(isp) 32
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#define MAX_MAILBOX 32
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/* if timeout == 0, then default timeout is picked */
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#define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */
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typedef struct {
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uint16_t param[MAX_MAILBOX];
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uint32_t ibits; /* bits to add for register copyin */
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uint32_t obits; /* bits to add for register copyout */
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uint32_t ibitm; /* bits to mask for register copyin */
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uint32_t obitm; /* bits to mask for register copyout */
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uint32_t logval; /* Bitmask of status codes to log */
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uint32_t timeout;
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uint32_t lineno;
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const char *func;
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} mbreg_t;
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#define MBSINIT(mbxp, code, loglev, timo) \
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ISP_MEMZERO((mbxp), sizeof (mbreg_t)); \
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(mbxp)->ibitm = ~0; \
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(mbxp)->obitm = ~0; \
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(mbxp)->param[0] = code; \
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(mbxp)->lineno = __LINE__; \
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(mbxp)->func = __func__; \
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(mbxp)->logval = loglev; \
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(mbxp)->timeout = timo
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/*
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* Defines for Interrupts
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*/
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#define ISP_INTS_ENABLED(isp) \
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(ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK)
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#define ISP_ENABLE_INTS(isp) \
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ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)
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#define ISP_DISABLE_INTS(isp) \
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ISP_WRITE(isp, BIU2400_ICR, 0)
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/*
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* NVRAM Definitions (PCI cards only)
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*/
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/*
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* Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum.
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*/
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#define ISP2400_NVRAM_PORT_ADDR(c) (0x100 * (c) + 0x80)
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#define ISP2400_NVRAM_SIZE 512
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#define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8))
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#define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8))
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#define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8))
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#define ISP2400_NVRAM_PORT_NAME(c) (\
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(((uint64_t)(c)[20]) << 56) | \
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(((uint64_t)(c)[21]) << 48) | \
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(((uint64_t)(c)[22]) << 40) | \
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(((uint64_t)(c)[23]) << 32) | \
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(((uint64_t)(c)[24]) << 24) | \
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(((uint64_t)(c)[25]) << 16) | \
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(((uint64_t)(c)[26]) << 8) | \
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(((uint64_t)(c)[27]) << 0))
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#define ISP2400_NVRAM_NODE_NAME(c) (\
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(((uint64_t)(c)[28]) << 56) | \
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(((uint64_t)(c)[29]) << 48) | \
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(((uint64_t)(c)[30]) << 40) | \
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(((uint64_t)(c)[31]) << 32) | \
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(((uint64_t)(c)[32]) << 24) | \
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(((uint64_t)(c)[33]) << 16) | \
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(((uint64_t)(c)[34]) << 8) | \
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(((uint64_t)(c)[35]) << 0))
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#define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8))
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#define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8))
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#define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8))
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#define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8))
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#define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \
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((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24))
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#define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \
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((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24))
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#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \
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((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24))
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/*
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* Qlogic FLT
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*/
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#define ISP24XX_BASE_ADDR 0x7ff00000
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#define ISP24XX_FLT_ADDR 0x11400
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#define ISP25XX_BASE_ADDR ISP24XX_BASE_ADDR
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#define ISP25XX_FLT_ADDR 0x50400
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#define ISP27XX_BASE_ADDR 0x7f800000
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#define ISP27XX_FLT_ADDR (0x3F1000 / 4)
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#define ISP28XX_BASE_ADDR 0x7f7d0000
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#define ISP28XX_FLT_ADDR (0x11000 / 4)
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#define FLT_HEADER_SIZE 8
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#define FLT_REGION_SIZE 16
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#define FLT_MAX_REGIONS 0xFF
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#define FLT_REGIONS_SIZE (FLT_REGION_SIZE * FLT_MAX_REGIONS)
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#define ISP2XXX_FLT_VERSION(c) ((c)[0] | ((c)[1] << 8))
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#define ISP2XXX_FLT_LENGTH(c) ((c)[2] | ((c)[3] << 8))
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#define ISP2XXX_FLT_CSUM(c) ((c)[4] | ((c)[5] << 8))
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#define ISP2XXX_FLT_REG_CODE(c, o) \
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((c)[0 + FLT_REGION_SIZE * o] | ((c)[1 + FLT_REGION_SIZE * o] << 8))
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#define ISP2XXX_FLT_REG_ATTR(c, o) ((c)[2 + FLT_REGION_SIZE * o])
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#define ISP2XXX_FLT_REG_RES(c, o) ((c)[3 + FLT_REGION_SIZE * o])
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#define ISP2XXX_FLT_REG_SIZE(c, o) (\
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((uint32_t)(c)[4 + FLT_REGION_SIZE * o] << 0) | \
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((uint32_t)(c)[5 + FLT_REGION_SIZE * o] << 8) | \
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((uint32_t)(c)[6 + FLT_REGION_SIZE * o] << 16) | \
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((uint32_t)(c)[7 + FLT_REGION_SIZE * o] << 24))
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#define ISP2XXX_FLT_REG_START(c, o) (\
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((uint32_t)(c)[8 + FLT_REGION_SIZE * o] << 0) | \
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((uint32_t)(c)[9 + FLT_REGION_SIZE * o] << 8) | \
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((uint32_t)(c)[10 + FLT_REGION_SIZE * o] << 16) | \
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((uint32_t)(c)[11 + FLT_REGION_SIZE * o] << 24))
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#define ISP2XXX_FLT_REG_END(c, o) (\
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((uint32_t)(c)[12 + FLT_REGION_SIZE * o] << 0) | \
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((uint32_t)(c)[13 + FLT_REGION_SIZE * o] << 8) | \
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((uint32_t)(c)[14 + FLT_REGION_SIZE * o] << 16) | \
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((uint32_t)(c)[15 + FLT_REGION_SIZE * o] << 24))
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struct flt_region {
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uint16_t code;
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uint8_t attribute;
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uint8_t reserved;
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uint32_t size;
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uint32_t start;
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uint32_t end;
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};
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#define FLT_REG_FW 0x01
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#define FLT_REG_BOOT_CODE 0x07
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#define FLT_REG_VPD_0 0x14
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#define FLT_REG_NVRAM_0 0x15
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#define FLT_REG_VPD_1 0x16
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#define FLT_REG_NVRAM_1 0x17
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#define FLT_REG_VPD_2 0xd4
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#define FLT_REG_NVRAM_2 0xd5
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#define FLT_REG_VPD_3 0xd6
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#define FLT_REG_NVRAM_3 0xd7
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#define FLT_REG_FDT 0x1a
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#define FLT_REG_FLT 0x1c
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#define FLT_REG_NPIV_CONF_0 0x29
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#define FLT_REG_NPIV_CONF_1 0x2a
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#define FLT_REG_GOLD_FW 0x2f
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#define FLT_REG_FCP_PRIO_0 0x87
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#define FLT_REG_FCP_PRIO_1 0x88
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/* 27xx */
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#define FLT_REG_IMG_PRI_27XX 0x95
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#define FLT_REG_IMG_SEC_27XX 0x96
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#define FLT_REG_FW_SEC_27XX 0x02
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#define FLT_REG_BOOTLOAD_SEC_27XX 0x9
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#define FLT_REG_VPD_SEC_27XX_0 0x50
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#define FLT_REG_VPD_SEC_27XX_1 0x52
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#define FLT_REG_VPD_SEC_27XX_2 0xd8
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#define FLT_REG_VPD_SEC_27XX_3 0xda
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/* 28xx */
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#define FLT_REG_AUX_IMG_PRI_28XX 0x125
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#define FLT_REG_AUX_IMG_SEC_28XX 0x126
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#define FLT_REG_NVRAM_SEC_28XX_0 0x10d
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#define FLT_REG_NVRAM_SEC_28XX_1 0x10f
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#define FLT_REG_NVRAM_SEC_28XX_2 0x111
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#define FLT_REG_NVRAM_SEC_28XX_3 0x113
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#define FLT_REG_VPD_SEC_28XX_0 0x10c
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#define FLT_REG_VPD_SEC_28XX_1 0x10e
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#define FLT_REG_VPD_SEC_28XX_2 0x110
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#define FLT_REG_VPD_SEC_28XX_3 0x112
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#endif /* _ISPREG_H */
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