532 lines
17 KiB
C
532 lines
17 KiB
C
/******************************************************************************
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Copyright (c) 2001-2017, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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#ifndef IXGBE_STANDALONE_BUILD
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#include "opt_inet.h"
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#include "opt_inet6.h"
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#include "opt_rss.h"
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#endif
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#include "ixgbe.h"
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/************************************************************************
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* Local Function prototypes
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************************************************************************/
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static int ixgbe_isc_txd_encap(void *, if_pkt_info_t);
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static void ixgbe_isc_txd_flush(void *, uint16_t, qidx_t);
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static int ixgbe_isc_txd_credits_update(void *, uint16_t, bool);
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static void ixgbe_isc_rxd_refill(void *, if_rxd_update_t);
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static void ixgbe_isc_rxd_flush(void *, uint16_t, uint8_t, qidx_t);
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static int ixgbe_isc_rxd_available(void *, uint16_t, qidx_t, qidx_t);
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static int ixgbe_isc_rxd_pkt_get(void *, if_rxd_info_t);
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static void ixgbe_rx_checksum(uint32_t, if_rxd_info_t, uint32_t);
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static int ixgbe_tx_ctx_setup(struct ixgbe_adv_tx_context_desc *,
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if_pkt_info_t);
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extern void ixgbe_if_enable_intr(if_ctx_t ctx);
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static int ixgbe_determine_rsstype(uint16_t pkt_info);
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struct if_txrx ixgbe_txrx = {
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.ift_txd_encap = ixgbe_isc_txd_encap,
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.ift_txd_flush = ixgbe_isc_txd_flush,
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.ift_txd_credits_update = ixgbe_isc_txd_credits_update,
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.ift_rxd_available = ixgbe_isc_rxd_available,
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.ift_rxd_pkt_get = ixgbe_isc_rxd_pkt_get,
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.ift_rxd_refill = ixgbe_isc_rxd_refill,
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.ift_rxd_flush = ixgbe_isc_rxd_flush,
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.ift_legacy_intr = NULL
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};
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/************************************************************************
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* ixgbe_tx_ctx_setup
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*
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* Advanced Context Descriptor setup for VLAN, CSUM or TSO
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*
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************************************************************************/
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static int
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ixgbe_tx_ctx_setup(struct ixgbe_adv_tx_context_desc *TXD, if_pkt_info_t pi)
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{
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uint32_t vlan_macip_lens, type_tucmd_mlhl;
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uint32_t olinfo_status, mss_l4len_idx, pktlen, offload;
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u8 ehdrlen;
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offload = true;
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olinfo_status = mss_l4len_idx = vlan_macip_lens = type_tucmd_mlhl = 0;
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/* VLAN MACLEN IPLEN */
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vlan_macip_lens |= (htole16(pi->ipi_vtag) << IXGBE_ADVTXD_VLAN_SHIFT);
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/*
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* Some of our VF devices need a context descriptor for every
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* packet. That means the ehdrlen needs to be non-zero in order
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* for the host driver not to flag a malicious event. The stack
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* will most likely populate this for all other reasons of why
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* this function was called.
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*/
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if (pi->ipi_ehdrlen == 0) {
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ehdrlen = ETHER_HDR_LEN;
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ehdrlen += (pi->ipi_vtag != 0) ? ETHER_VLAN_ENCAP_LEN : 0;
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} else
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ehdrlen = pi->ipi_ehdrlen;
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vlan_macip_lens |= ehdrlen << IXGBE_ADVTXD_MACLEN_SHIFT;
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pktlen = pi->ipi_len;
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/* First check if TSO is to be used */
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if (pi->ipi_csum_flags & CSUM_TSO) {
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/* This is used in the transmit desc in encap */
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pktlen = pi->ipi_len - ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen;
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mss_l4len_idx |= (pi->ipi_tso_segsz << IXGBE_ADVTXD_MSS_SHIFT);
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mss_l4len_idx |= (pi->ipi_tcp_hlen << IXGBE_ADVTXD_L4LEN_SHIFT);
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}
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olinfo_status |= pktlen << IXGBE_ADVTXD_PAYLEN_SHIFT;
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if (pi->ipi_flags & IPI_TX_IPV4) {
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type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
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/* Tell transmit desc to also do IPv4 checksum. */
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if (pi->ipi_csum_flags & (CSUM_IP|CSUM_TSO))
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olinfo_status |= IXGBE_TXD_POPTS_IXSM << 8;
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} else if (pi->ipi_flags & IPI_TX_IPV6)
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type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV6;
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else
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offload = false;
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vlan_macip_lens |= pi->ipi_ip_hlen;
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switch (pi->ipi_ipproto) {
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case IPPROTO_TCP:
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if (pi->ipi_csum_flags & (CSUM_IP_TCP | CSUM_IP6_TCP | CSUM_TSO))
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type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
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else
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offload = false;
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break;
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case IPPROTO_UDP:
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if (pi->ipi_csum_flags & (CSUM_IP_UDP | CSUM_IP6_UDP))
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type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP;
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else
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offload = false;
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break;
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case IPPROTO_SCTP:
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if (pi->ipi_csum_flags & (CSUM_IP_SCTP | CSUM_IP6_SCTP))
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type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
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else
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offload = false;
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break;
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default:
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offload = false;
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break;
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}
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/* Insert L4 checksum into data descriptors */
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if (offload)
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olinfo_status |= IXGBE_TXD_POPTS_TXSM << 8;
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type_tucmd_mlhl |= IXGBE_ADVTXD_DCMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
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/* Now copy bits into descriptor */
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TXD->vlan_macip_lens = htole32(vlan_macip_lens);
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TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
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TXD->seqnum_seed = htole32(0);
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TXD->mss_l4len_idx = htole32(mss_l4len_idx);
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return (olinfo_status);
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} /* ixgbe_tx_ctx_setup */
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/************************************************************************
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* ixgbe_isc_txd_encap
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************************************************************************/
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static int
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ixgbe_isc_txd_encap(void *arg, if_pkt_info_t pi)
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{
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struct ixgbe_softc *sc = arg;
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if_softc_ctx_t scctx = sc->shared;
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struct ix_tx_queue *que = &sc->tx_queues[pi->ipi_qsidx];
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struct tx_ring *txr = &que->txr;
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int nsegs = pi->ipi_nsegs;
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bus_dma_segment_t *segs = pi->ipi_segs;
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union ixgbe_adv_tx_desc *txd = NULL;
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struct ixgbe_adv_tx_context_desc *TXD;
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int i, j, first, pidx_last;
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uint32_t olinfo_status, cmd, flags;
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qidx_t ntxd;
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cmd = (IXGBE_ADVTXD_DTYP_DATA |
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IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT);
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if (pi->ipi_mflags & M_VLANTAG)
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cmd |= IXGBE_ADVTXD_DCMD_VLE;
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i = first = pi->ipi_pidx;
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flags = (pi->ipi_flags & IPI_TX_INTR) ? IXGBE_TXD_CMD_RS : 0;
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ntxd = scctx->isc_ntxd[0];
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TXD = (struct ixgbe_adv_tx_context_desc *) &txr->tx_base[first];
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if ((pi->ipi_csum_flags & CSUM_OFFLOAD) ||
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(sc->feat_en & IXGBE_FEATURE_NEEDS_CTXD) ||
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pi->ipi_vtag) {
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/*********************************************
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* Set up the appropriate offload context
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* this will consume the first descriptor
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*********************************************/
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olinfo_status = ixgbe_tx_ctx_setup(TXD, pi);
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if (pi->ipi_csum_flags & CSUM_TSO) {
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cmd |= IXGBE_ADVTXD_DCMD_TSE;
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++txr->tso_tx;
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}
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if (++i == scctx->isc_ntxd[0])
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i = 0;
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} else {
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/* Indicate the whole packet as payload when not doing TSO */
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olinfo_status = pi->ipi_len << IXGBE_ADVTXD_PAYLEN_SHIFT;
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}
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olinfo_status |= IXGBE_ADVTXD_CC;
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pidx_last = 0;
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for (j = 0; j < nsegs; j++) {
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bus_size_t seglen;
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txd = &txr->tx_base[i];
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seglen = segs[j].ds_len;
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txd->read.buffer_addr = htole64(segs[j].ds_addr);
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txd->read.cmd_type_len = htole32(cmd | seglen);
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txd->read.olinfo_status = htole32(olinfo_status);
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pidx_last = i;
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if (++i == scctx->isc_ntxd[0]) {
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i = 0;
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}
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}
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if (flags) {
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txr->tx_rsq[txr->tx_rs_pidx] = pidx_last;
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txr->tx_rs_pidx = (txr->tx_rs_pidx + 1) & (ntxd - 1);
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}
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txd->read.cmd_type_len |= htole32(IXGBE_TXD_CMD_EOP | flags);
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txr->bytes += pi->ipi_len;
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pi->ipi_new_pidx = i;
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++txr->total_packets;
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return (0);
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} /* ixgbe_isc_txd_encap */
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/************************************************************************
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* ixgbe_isc_txd_flush
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************************************************************************/
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static void
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ixgbe_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx)
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{
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struct ixgbe_softc *sc = arg;
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struct ix_tx_queue *que = &sc->tx_queues[txqid];
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struct tx_ring *txr = &que->txr;
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IXGBE_WRITE_REG(&sc->hw, txr->tail, pidx);
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} /* ixgbe_isc_txd_flush */
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/************************************************************************
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* ixgbe_isc_txd_credits_update
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************************************************************************/
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static int
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ixgbe_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear)
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{
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struct ixgbe_softc *sc = arg;
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if_softc_ctx_t scctx = sc->shared;
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struct ix_tx_queue *que = &sc->tx_queues[txqid];
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struct tx_ring *txr = &que->txr;
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qidx_t processed = 0;
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int updated;
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qidx_t cur, prev, ntxd, rs_cidx;
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int32_t delta;
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uint8_t status;
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rs_cidx = txr->tx_rs_cidx;
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if (rs_cidx == txr->tx_rs_pidx)
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return (0);
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cur = txr->tx_rsq[rs_cidx];
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status = txr->tx_base[cur].wb.status;
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updated = !!(status & IXGBE_TXD_STAT_DD);
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if (!updated)
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return (0);
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/* If clear is false just let caller know that there
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* are descriptors to reclaim */
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if (!clear)
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return (1);
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prev = txr->tx_cidx_processed;
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ntxd = scctx->isc_ntxd[0];
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do {
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MPASS(prev != cur);
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delta = (int32_t)cur - (int32_t)prev;
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if (delta < 0)
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delta += ntxd;
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MPASS(delta > 0);
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processed += delta;
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prev = cur;
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rs_cidx = (rs_cidx + 1) & (ntxd - 1);
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if (rs_cidx == txr->tx_rs_pidx)
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break;
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cur = txr->tx_rsq[rs_cidx];
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status = txr->tx_base[cur].wb.status;
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} while ((status & IXGBE_TXD_STAT_DD));
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txr->tx_rs_cidx = rs_cidx;
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txr->tx_cidx_processed = prev;
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return (processed);
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} /* ixgbe_isc_txd_credits_update */
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/************************************************************************
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* ixgbe_isc_rxd_refill
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************************************************************************/
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static void
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ixgbe_isc_rxd_refill(void *arg, if_rxd_update_t iru)
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{
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struct ixgbe_softc *sc = arg;
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struct ix_rx_queue *que = &sc->rx_queues[iru->iru_qsidx];
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struct rx_ring *rxr = &que->rxr;
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uint64_t *paddrs;
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int i;
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uint32_t next_pidx, pidx;
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uint16_t count;
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paddrs = iru->iru_paddrs;
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pidx = iru->iru_pidx;
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count = iru->iru_count;
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for (i = 0, next_pidx = pidx; i < count; i++) {
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rxr->rx_base[next_pidx].read.pkt_addr = htole64(paddrs[i]);
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if (++next_pidx == sc->shared->isc_nrxd[0])
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next_pidx = 0;
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}
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} /* ixgbe_isc_rxd_refill */
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/************************************************************************
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* ixgbe_isc_rxd_flush
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************************************************************************/
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static void
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ixgbe_isc_rxd_flush(void *arg, uint16_t qsidx, uint8_t flidx __unused, qidx_t pidx)
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{
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struct ixgbe_softc *sc = arg;
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struct ix_rx_queue *que = &sc->rx_queues[qsidx];
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struct rx_ring *rxr = &que->rxr;
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IXGBE_WRITE_REG(&sc->hw, rxr->tail, pidx);
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} /* ixgbe_isc_rxd_flush */
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/************************************************************************
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* ixgbe_isc_rxd_available
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************************************************************************/
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static int
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ixgbe_isc_rxd_available(void *arg, uint16_t qsidx, qidx_t pidx, qidx_t budget)
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{
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struct ixgbe_softc *sc = arg;
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struct ix_rx_queue *que = &sc->rx_queues[qsidx];
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struct rx_ring *rxr = &que->rxr;
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union ixgbe_adv_rx_desc *rxd;
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uint32_t staterr;
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int cnt, i, nrxd;
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nrxd = sc->shared->isc_nrxd[0];
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for (cnt = 0, i = pidx; cnt < nrxd && cnt <= budget;) {
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rxd = &rxr->rx_base[i];
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staterr = le32toh(rxd->wb.upper.status_error);
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if ((staterr & IXGBE_RXD_STAT_DD) == 0)
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break;
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if (++i == nrxd)
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i = 0;
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if (staterr & IXGBE_RXD_STAT_EOP)
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cnt++;
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}
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return (cnt);
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} /* ixgbe_isc_rxd_available */
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/************************************************************************
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* ixgbe_isc_rxd_pkt_get
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*
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* Routine sends data which has been dma'ed into host memory
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* to upper layer. Initialize ri structure.
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*
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* Returns 0 upon success, errno on failure
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************************************************************************/
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static int
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ixgbe_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
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{
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struct ixgbe_softc *sc = arg;
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if_softc_ctx_t scctx = sc->shared;
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struct ix_rx_queue *que = &sc->rx_queues[ri->iri_qsidx];
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struct rx_ring *rxr = &que->rxr;
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union ixgbe_adv_rx_desc *rxd;
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uint16_t pkt_info, len, cidx, i;
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uint32_t ptype;
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uint32_t staterr = 0;
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bool eop;
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i = 0;
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cidx = ri->iri_cidx;
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do {
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rxd = &rxr->rx_base[cidx];
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staterr = le32toh(rxd->wb.upper.status_error);
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pkt_info = le16toh(rxd->wb.lower.lo_dword.hs_rss.pkt_info);
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/* Error Checking then decrement count */
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MPASS ((staterr & IXGBE_RXD_STAT_DD) != 0);
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len = le16toh(rxd->wb.upper.length);
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ptype = le32toh(rxd->wb.lower.lo_dword.data) &
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IXGBE_RXDADV_PKTTYPE_MASK;
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ri->iri_len += len;
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rxr->bytes += len;
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rxd->wb.upper.status_error = 0;
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eop = ((staterr & IXGBE_RXD_STAT_EOP) != 0);
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/* Make sure bad packets are discarded */
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if (eop && (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) != 0) {
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if (sc->feat_en & IXGBE_FEATURE_VF)
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if_inc_counter(ri->iri_ifp, IFCOUNTER_IERRORS, 1);
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rxr->rx_discarded++;
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return (EBADMSG);
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}
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ri->iri_frags[i].irf_flid = 0;
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ri->iri_frags[i].irf_idx = cidx;
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ri->iri_frags[i].irf_len = len;
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if (++cidx == sc->shared->isc_nrxd[0])
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cidx = 0;
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i++;
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/* even a 16K packet shouldn't consume more than 8 clusters */
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MPASS(i < 9);
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} while (!eop);
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rxr->rx_packets++;
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rxr->packets++;
|
|
rxr->rx_bytes += ri->iri_len;
|
|
|
|
if ((scctx->isc_capenable & IFCAP_RXCSUM) != 0)
|
|
ixgbe_rx_checksum(staterr, ri, ptype);
|
|
|
|
ri->iri_flowid = le32toh(rxd->wb.lower.hi_dword.rss);
|
|
ri->iri_rsstype = ixgbe_determine_rsstype(pkt_info);
|
|
if ((sc->feat_en & IXGBE_FEATURE_RSS) == 0) {
|
|
if (ri->iri_rsstype == M_HASHTYPE_OPAQUE)
|
|
ri->iri_rsstype = M_HASHTYPE_NONE;
|
|
else
|
|
ri->iri_rsstype = M_HASHTYPE_OPAQUE_HASH;
|
|
}
|
|
if ((rxr->vtag_strip) && (staterr & IXGBE_RXD_STAT_VP)) {
|
|
ri->iri_vtag = le16toh(rxd->wb.upper.vlan);
|
|
ri->iri_flags |= M_VLANTAG;
|
|
}
|
|
|
|
ri->iri_nfrags = i;
|
|
return (0);
|
|
} /* ixgbe_isc_rxd_pkt_get */
|
|
|
|
/************************************************************************
|
|
* ixgbe_rx_checksum
|
|
*
|
|
* Verify that the hardware indicated that the checksum is valid.
|
|
* Inform the stack about the status of checksum so that stack
|
|
* doesn't spend time verifying the checksum.
|
|
************************************************************************/
|
|
static void
|
|
ixgbe_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype)
|
|
{
|
|
uint16_t status = (uint16_t)staterr;
|
|
uint8_t errors = (uint8_t)(staterr >> 24);
|
|
|
|
/* If there is a layer 3 or 4 error we are done */
|
|
if (__predict_false(errors & (IXGBE_RXD_ERR_IPE | IXGBE_RXD_ERR_TCPE)))
|
|
return;
|
|
|
|
/* IP Checksum Good */
|
|
if (status & IXGBE_RXD_STAT_IPCS)
|
|
ri->iri_csum_flags = (CSUM_IP_CHECKED | CSUM_IP_VALID);
|
|
|
|
/* Valid L4E checksum */
|
|
if (__predict_true(status & IXGBE_RXD_STAT_L4CS)) {
|
|
/* SCTP header present. */
|
|
if (__predict_false((ptype & IXGBE_RXDADV_PKTTYPE_ETQF) == 0 &&
|
|
(ptype & IXGBE_RXDADV_PKTTYPE_SCTP) != 0)) {
|
|
ri->iri_csum_flags |= CSUM_SCTP_VALID;
|
|
} else {
|
|
ri->iri_csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
|
|
ri->iri_csum_data = htons(0xffff);
|
|
}
|
|
}
|
|
} /* ixgbe_rx_checksum */
|
|
|
|
/************************************************************************
|
|
* ixgbe_determine_rsstype
|
|
*
|
|
* Parse the packet type to determine the appropriate hash
|
|
************************************************************************/
|
|
static int
|
|
ixgbe_determine_rsstype(uint16_t pkt_info)
|
|
{
|
|
switch (pkt_info & IXGBE_RXDADV_RSSTYPE_MASK) {
|
|
case IXGBE_RXDADV_RSSTYPE_IPV4_TCP:
|
|
return M_HASHTYPE_RSS_TCP_IPV4;
|
|
case IXGBE_RXDADV_RSSTYPE_IPV4:
|
|
return M_HASHTYPE_RSS_IPV4;
|
|
case IXGBE_RXDADV_RSSTYPE_IPV6_TCP:
|
|
return M_HASHTYPE_RSS_TCP_IPV6;
|
|
case IXGBE_RXDADV_RSSTYPE_IPV6_EX:
|
|
return M_HASHTYPE_RSS_IPV6_EX;
|
|
case IXGBE_RXDADV_RSSTYPE_IPV6:
|
|
return M_HASHTYPE_RSS_IPV6;
|
|
case IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX:
|
|
return M_HASHTYPE_RSS_TCP_IPV6_EX;
|
|
case IXGBE_RXDADV_RSSTYPE_IPV4_UDP:
|
|
return M_HASHTYPE_RSS_UDP_IPV4;
|
|
case IXGBE_RXDADV_RSSTYPE_IPV6_UDP:
|
|
return M_HASHTYPE_RSS_UDP_IPV6;
|
|
case IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX:
|
|
return M_HASHTYPE_RSS_UDP_IPV6_EX;
|
|
default:
|
|
return M_HASHTYPE_OPAQUE;
|
|
}
|
|
} /* ixgbe_determine_rsstype */
|