1130 lines
32 KiB
C
1130 lines
32 KiB
C
/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (c) 2000
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* Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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/*
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* Driver for the Broadcom BCM54xx/57xx 1000baseTX PHY.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <sys/taskqueue.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/ethernet.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include <dev/mii/brgphyreg.h>
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#include <net/if_arp.h>
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#include <machine/bus.h>
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#include <dev/bge/if_bgereg.h>
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#include <dev/bce/if_bcereg.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include "miibus_if.h"
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static int brgphy_probe(device_t);
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static int brgphy_attach(device_t);
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struct brgphy_softc {
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struct mii_softc mii_sc;
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int serdes_flags; /* Keeps track of the serdes type used */
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#define BRGPHY_5706S 0x0001
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#define BRGPHY_5708S 0x0002
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#define BRGPHY_NOANWAIT 0x0004
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#define BRGPHY_5709S 0x0008
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int bce_phy_flags; /* PHY flags transferred from the MAC driver */
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};
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static device_method_t brgphy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, brgphy_probe),
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DEVMETHOD(device_attach, brgphy_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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};
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static driver_t brgphy_driver = {
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"brgphy",
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brgphy_methods,
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sizeof(struct brgphy_softc)
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};
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DRIVER_MODULE(brgphy, miibus, brgphy_driver, 0, 0);
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static int brgphy_service(struct mii_softc *, struct mii_data *, int);
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static void brgphy_setmedia(struct mii_softc *, int);
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static void brgphy_status(struct mii_softc *);
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static void brgphy_mii_phy_auto(struct mii_softc *, int);
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static void brgphy_reset(struct mii_softc *);
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static void brgphy_enable_loopback(struct mii_softc *);
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static void bcm5401_load_dspcode(struct mii_softc *);
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static void bcm5411_load_dspcode(struct mii_softc *);
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static void bcm54k2_load_dspcode(struct mii_softc *);
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static void brgphy_fixup_5704_a0_bug(struct mii_softc *);
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static void brgphy_fixup_adc_bug(struct mii_softc *);
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static void brgphy_fixup_adjust_trim(struct mii_softc *);
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static void brgphy_fixup_ber_bug(struct mii_softc *);
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static void brgphy_fixup_crc_bug(struct mii_softc *);
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static void brgphy_fixup_jitter_bug(struct mii_softc *);
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static void brgphy_ethernet_wirespeed(struct mii_softc *);
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static void brgphy_bcm54xx_clock_delay(struct mii_softc *);
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static void brgphy_jumbo_settings(struct mii_softc *, u_long);
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static const struct mii_phydesc brgphys[] = {
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MII_PHY_DESC(BROADCOM, BCM5400),
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MII_PHY_DESC(BROADCOM, BCM5401),
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MII_PHY_DESC(BROADCOM, BCM5402),
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MII_PHY_DESC(BROADCOM, BCM5411),
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MII_PHY_DESC(BROADCOM, BCM5404),
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MII_PHY_DESC(BROADCOM, BCM5424),
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MII_PHY_DESC(BROADCOM, BCM54K2),
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MII_PHY_DESC(BROADCOM, BCM5701),
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MII_PHY_DESC(BROADCOM, BCM5703),
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MII_PHY_DESC(BROADCOM, BCM5704),
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MII_PHY_DESC(BROADCOM, BCM5705),
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MII_PHY_DESC(BROADCOM, BCM5706),
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MII_PHY_DESC(BROADCOM, BCM5714),
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MII_PHY_DESC(BROADCOM, BCM5421),
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MII_PHY_DESC(BROADCOM, BCM5750),
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MII_PHY_DESC(BROADCOM, BCM5752),
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MII_PHY_DESC(BROADCOM, BCM5780),
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MII_PHY_DESC(BROADCOM, BCM5708C),
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MII_PHY_DESC(BROADCOM, BCM5466),
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MII_PHY_DESC(BROADCOM2, BCM5478),
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MII_PHY_DESC(BROADCOM2, BCM5488),
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MII_PHY_DESC(BROADCOM2, BCM5482),
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MII_PHY_DESC(BROADCOM2, BCM5708S),
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MII_PHY_DESC(BROADCOM2, BCM5709C),
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MII_PHY_DESC(BROADCOM2, BCM5709S),
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MII_PHY_DESC(BROADCOM2, BCM5709CAX),
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MII_PHY_DESC(BROADCOM2, BCM5722),
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MII_PHY_DESC(BROADCOM2, BCM5755),
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MII_PHY_DESC(BROADCOM2, BCM5754),
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MII_PHY_DESC(BROADCOM2, BCM5761),
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MII_PHY_DESC(BROADCOM2, BCM5784),
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#ifdef notyet /* better handled by ukphy(4) until WARs are implemented */
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MII_PHY_DESC(BROADCOM2, BCM5785),
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#endif
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MII_PHY_DESC(BROADCOM3, BCM54616S),
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MII_PHY_DESC(BROADCOM3, BCM54618SE),
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MII_PHY_DESC(BROADCOM3, BCM5717C),
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MII_PHY_DESC(BROADCOM3, BCM5719C),
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MII_PHY_DESC(BROADCOM3, BCM5720C),
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MII_PHY_DESC(BROADCOM3, BCM57765),
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MII_PHY_DESC(BROADCOM3, BCM57780),
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MII_PHY_DESC(BROADCOM4, BCM54213PE),
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MII_PHY_DESC(BROADCOM4, BCM5725C),
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MII_PHY_DESC(xxBROADCOM_ALT1, BCM5906),
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MII_PHY_END
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};
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static const struct mii_phy_funcs brgphy_funcs = {
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brgphy_service,
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brgphy_status,
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brgphy_reset
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};
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static const struct hs21_type {
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const uint32_t id;
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const char *prod;
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} hs21_type_lists[] = {
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{ 0x57081021, "IBM eServer BladeCenter HS21" },
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{ 0x57081011, "IBM eServer BladeCenter HS21 -[8853PAU]-" },
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};
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static int
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detect_hs21(struct bce_softc *bce_sc)
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{
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char *sysenv;
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int found, i;
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found = 0;
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sysenv = kern_getenv("smbios.system.product");
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if (sysenv == NULL)
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return (found);
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for (i = 0; i < nitems(hs21_type_lists); i++) {
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if (bce_sc->bce_chipid == hs21_type_lists[i].id &&
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strncmp(sysenv, hs21_type_lists[i].prod,
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strlen(hs21_type_lists[i].prod)) == 0) {
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found++;
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break;
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}
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}
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freeenv(sysenv);
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return (found);
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}
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/* Search for our PHY in the list of known PHYs */
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static int
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brgphy_probe(device_t dev)
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{
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return (mii_phy_dev_probe(dev, brgphys, BUS_PROBE_DEFAULT));
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}
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/* Attach the PHY to the MII bus */
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static int
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brgphy_attach(device_t dev)
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{
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struct brgphy_softc *bsc;
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struct bge_softc *bge_sc = NULL;
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struct bce_softc *bce_sc = NULL;
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struct mii_softc *sc;
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bsc = device_get_softc(dev);
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sc = &bsc->mii_sc;
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mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
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&brgphy_funcs, 0);
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bsc->serdes_flags = 0;
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/* Find the MAC driver associated with this PHY. */
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if (mii_dev_mac_match(dev, "bge"))
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bge_sc = mii_dev_mac_softc(dev);
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else if (mii_dev_mac_match(dev, "bce"))
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bce_sc = mii_dev_mac_softc(dev);
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/* Handle any special cases based on the PHY ID */
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switch (sc->mii_mpd_oui) {
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case MII_OUI_BROADCOM:
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switch (sc->mii_mpd_model) {
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case MII_MODEL_BROADCOM_BCM5706:
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case MII_MODEL_BROADCOM_BCM5714:
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/*
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* The 5464 PHY used in the 5706 supports both copper
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* and fiber interfaces over GMII. Need to check the
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* shadow registers to see which mode is actually
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* in effect, and therefore whether we have 5706C or
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* 5706S.
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*/
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PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C,
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BRGPHY_SHADOW_1C_MODE_CTRL);
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if (PHY_READ(sc, BRGPHY_MII_SHADOW_1C) &
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BRGPHY_SHADOW_1C_ENA_1000X) {
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bsc->serdes_flags |= BRGPHY_5706S;
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sc->mii_flags |= MIIF_HAVEFIBER;
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}
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break;
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}
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break;
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case MII_OUI_BROADCOM2:
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switch (sc->mii_mpd_model) {
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case MII_MODEL_BROADCOM2_BCM5708S:
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bsc->serdes_flags |= BRGPHY_5708S;
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sc->mii_flags |= MIIF_HAVEFIBER;
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break;
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case MII_MODEL_BROADCOM2_BCM5709S:
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/*
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* XXX
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* 5720S and 5709S shares the same PHY id.
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* Assume 5720S PHY if parent device is bge(4).
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*/
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if (bge_sc != NULL)
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bsc->serdes_flags |= BRGPHY_5708S;
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else
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bsc->serdes_flags |= BRGPHY_5709S;
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sc->mii_flags |= MIIF_HAVEFIBER;
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break;
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}
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break;
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}
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PHY_RESET(sc);
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/* Read the PHY's capabilities. */
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sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
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device_printf(dev, " ");
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/* Add the supported media types */
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if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
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mii_phy_add_media(sc);
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printf("\n");
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} else {
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sc->mii_anegticks = MII_ANEGTICKS_GIGE;
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ifmedia_add(&sc->mii_pdata->mii_media,
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IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, sc->mii_inst),
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0, NULL);
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printf("1000baseSX-FDX, ");
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/*
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* 2.5G support is a software enabled feature
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* on the 5708S and 5709S.
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*/
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if (bce_sc && (bce_sc->bce_phy_flags &
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BCE_PHY_2_5G_CAPABLE_FLAG)) {
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ifmedia_add(&sc->mii_pdata->mii_media,
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IFM_MAKEWORD(IFM_ETHER, IFM_2500_SX, IFM_FDX,
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sc->mii_inst), 0, NULL);
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printf("2500baseSX-FDX, ");
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} else if ((bsc->serdes_flags & BRGPHY_5708S) && bce_sc &&
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(detect_hs21(bce_sc) != 0)) {
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/*
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* There appears to be certain silicon revision
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* in IBM HS21 blades that is having issues with
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* this driver wating for the auto-negotiation to
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* complete. This happens with a specific chip id
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* only and when the 1000baseSX-FDX is the only
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* mode. Workaround this issue since it's unlikely
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* to be ever addressed.
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*/
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printf("auto-neg workaround, ");
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bsc->serdes_flags |= BRGPHY_NOANWAIT;
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}
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ifmedia_add(&sc->mii_pdata->mii_media, IFM_MAKEWORD(IFM_ETHER,
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IFM_AUTO, 0, sc->mii_inst), 0, NULL);
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printf("auto\n");
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}
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return (0);
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}
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static int
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brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int val;
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switch (cmd) {
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case MII_POLLSTAT:
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break;
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case MII_MEDIACHG:
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/* Todo: Why is this here? Is it really needed? */
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PHY_RESET(sc); /* XXX hardware bug work-around */
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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brgphy_mii_phy_auto(sc, ife->ifm_media);
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break;
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case IFM_2500_SX:
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case IFM_1000_SX:
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case IFM_1000_T:
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case IFM_100_TX:
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case IFM_10_T:
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brgphy_setmedia(sc, ife->ifm_media);
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break;
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default:
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return (EINVAL);
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}
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break;
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case MII_TICK:
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/* Bail if autoneg isn't in process. */
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
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sc->mii_ticks = 0;
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break;
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}
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/*
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process.
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*/
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val = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
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if (val & BMSR_LINK) {
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sc->mii_ticks = 0; /* Reset autoneg timer. */
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break;
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}
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/* Announce link loss right after it happens. */
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if (sc->mii_ticks++ == 0)
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break;
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/* Only retry autonegotiation every mii_anegticks seconds. */
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if (sc->mii_ticks <= sc->mii_anegticks)
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break;
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/* Retry autonegotiation */
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sc->mii_ticks = 0;
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brgphy_mii_phy_auto(sc, ife->ifm_media);
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break;
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}
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/* Update the media status. */
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PHY_STATUS(sc);
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/*
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* Callback if something changed. Note that we need to poke
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* the DSP on the Broadcom PHYs if the media changes.
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*/
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if (sc->mii_media_active != mii->mii_media_active ||
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sc->mii_media_status != mii->mii_media_status ||
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cmd == MII_MEDIACHG) {
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switch (sc->mii_mpd_oui) {
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case MII_OUI_BROADCOM:
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switch (sc->mii_mpd_model) {
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case MII_MODEL_BROADCOM_BCM5400:
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bcm5401_load_dspcode(sc);
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break;
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case MII_MODEL_BROADCOM_BCM5401:
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if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
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bcm5401_load_dspcode(sc);
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break;
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case MII_MODEL_BROADCOM_BCM5411:
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bcm5411_load_dspcode(sc);
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break;
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case MII_MODEL_BROADCOM_BCM54K2:
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bcm54k2_load_dspcode(sc);
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break;
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}
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break;
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case MII_OUI_BROADCOM4:
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switch (sc->mii_mpd_model) {
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case MII_MODEL_BROADCOM4_BCM54213PE:
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brgphy_bcm54xx_clock_delay(sc);
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break;
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}
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}
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}
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mii_phy_update(sc, cmd);
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return (0);
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}
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|
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/****************************************************************************/
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/* Sets the PHY link speed. */
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/* */
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/* Returns: */
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/* None */
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/****************************************************************************/
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static void
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brgphy_setmedia(struct mii_softc *sc, int media)
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{
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int bmcr = 0, gig;
|
|
|
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switch (IFM_SUBTYPE(media)) {
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case IFM_2500_SX:
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break;
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case IFM_1000_SX:
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case IFM_1000_T:
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bmcr = BRGPHY_S1000;
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break;
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case IFM_100_TX:
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bmcr = BRGPHY_S100;
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break;
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case IFM_10_T:
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default:
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|
bmcr = BRGPHY_S10;
|
|
break;
|
|
}
|
|
|
|
if ((media & IFM_FDX) != 0) {
|
|
bmcr |= BRGPHY_BMCR_FDX;
|
|
gig = BRGPHY_1000CTL_AFD;
|
|
} else {
|
|
gig = BRGPHY_1000CTL_AHD;
|
|
}
|
|
|
|
/* Force loopback to disconnect PHY from Ethernet medium. */
|
|
brgphy_enable_loopback(sc);
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
|
|
PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
|
|
|
|
if (IFM_SUBTYPE(media) != IFM_1000_T &&
|
|
IFM_SUBTYPE(media) != IFM_1000_SX) {
|
|
PHY_WRITE(sc, BRGPHY_MII_BMCR, bmcr);
|
|
return;
|
|
}
|
|
|
|
if (IFM_SUBTYPE(media) == IFM_1000_T) {
|
|
gig |= BRGPHY_1000CTL_MSE;
|
|
if ((media & IFM_ETH_MASTER) != 0)
|
|
gig |= BRGPHY_1000CTL_MSC;
|
|
}
|
|
PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
|
|
PHY_WRITE(sc, BRGPHY_MII_BMCR,
|
|
bmcr | BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
|
|
}
|
|
|
|
/****************************************************************************/
|
|
/* Set the media status based on the PHY settings. */
|
|
/* */
|
|
/* Returns: */
|
|
/* None */
|
|
/****************************************************************************/
|
|
static void
|
|
brgphy_status(struct mii_softc *sc)
|
|
{
|
|
struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
|
|
struct mii_data *mii = sc->mii_pdata;
|
|
int aux, bmcr, bmsr, val, xstat;
|
|
u_int flowstat;
|
|
|
|
mii->mii_media_status = IFM_AVALID;
|
|
mii->mii_media_active = IFM_ETHER;
|
|
|
|
bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
|
|
bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
|
|
|
|
if (bmcr & BRGPHY_BMCR_LOOP) {
|
|
mii->mii_media_active |= IFM_LOOP;
|
|
}
|
|
|
|
if ((bmcr & BRGPHY_BMCR_AUTOEN) &&
|
|
(bmsr & BRGPHY_BMSR_ACOMP) == 0 &&
|
|
(bsc->serdes_flags & BRGPHY_NOANWAIT) == 0) {
|
|
/* Erg, still trying, I guess... */
|
|
mii->mii_media_active |= IFM_NONE;
|
|
return;
|
|
}
|
|
|
|
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
|
/*
|
|
* NB: reading the ANAR, ANLPAR or 1000STS after the AUXSTS
|
|
* wedges at least the PHY of BCM5704 (but not others).
|
|
*/
|
|
flowstat = mii_phy_flowstatus(sc);
|
|
xstat = PHY_READ(sc, BRGPHY_MII_1000STS);
|
|
aux = PHY_READ(sc, BRGPHY_MII_AUXSTS);
|
|
|
|
/* If copper link is up, get the negotiated speed/duplex. */
|
|
if (aux & BRGPHY_AUXSTS_LINK) {
|
|
mii->mii_media_status |= IFM_ACTIVE;
|
|
switch (aux & BRGPHY_AUXSTS_AN_RES) {
|
|
case BRGPHY_RES_1000FD:
|
|
mii->mii_media_active |= IFM_1000_T | IFM_FDX; break;
|
|
case BRGPHY_RES_1000HD:
|
|
mii->mii_media_active |= IFM_1000_T | IFM_HDX; break;
|
|
case BRGPHY_RES_100FD:
|
|
mii->mii_media_active |= IFM_100_TX | IFM_FDX; break;
|
|
case BRGPHY_RES_100T4:
|
|
mii->mii_media_active |= IFM_100_T4; break;
|
|
case BRGPHY_RES_100HD:
|
|
mii->mii_media_active |= IFM_100_TX | IFM_HDX; break;
|
|
case BRGPHY_RES_10FD:
|
|
mii->mii_media_active |= IFM_10_T | IFM_FDX; break;
|
|
case BRGPHY_RES_10HD:
|
|
mii->mii_media_active |= IFM_10_T | IFM_HDX; break;
|
|
default:
|
|
mii->mii_media_active |= IFM_NONE; break;
|
|
}
|
|
|
|
if ((mii->mii_media_active & IFM_FDX) != 0)
|
|
mii->mii_media_active |= flowstat;
|
|
|
|
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T &&
|
|
(xstat & BRGPHY_1000STS_MSR) != 0)
|
|
mii->mii_media_active |= IFM_ETH_MASTER;
|
|
}
|
|
} else {
|
|
/* Todo: Add support for flow control. */
|
|
/* If serdes link is up, get the negotiated speed/duplex. */
|
|
if (bmsr & BRGPHY_BMSR_LINK) {
|
|
mii->mii_media_status |= IFM_ACTIVE;
|
|
}
|
|
|
|
/* Check the link speed/duplex based on the PHY type. */
|
|
if (bsc->serdes_flags & BRGPHY_5706S) {
|
|
mii->mii_media_active |= IFM_1000_SX;
|
|
|
|
/* If autoneg enabled, read negotiated duplex settings */
|
|
if (bmcr & BRGPHY_BMCR_AUTOEN) {
|
|
val = PHY_READ(sc, BRGPHY_SERDES_ANAR) & PHY_READ(sc, BRGPHY_SERDES_ANLPAR);
|
|
if (val & BRGPHY_SERDES_ANAR_FDX)
|
|
mii->mii_media_active |= IFM_FDX;
|
|
else
|
|
mii->mii_media_active |= IFM_HDX;
|
|
}
|
|
} else if (bsc->serdes_flags & BRGPHY_5708S) {
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
|
|
xstat = PHY_READ(sc, BRGPHY_5708S_PG0_1000X_STAT1);
|
|
|
|
/* Check for MRBE auto-negotiated speed results. */
|
|
switch (xstat & BRGPHY_5708S_PG0_1000X_STAT1_SPEED_MASK) {
|
|
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_10:
|
|
mii->mii_media_active |= IFM_10_FL; break;
|
|
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_100:
|
|
mii->mii_media_active |= IFM_100_FX; break;
|
|
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_1G:
|
|
mii->mii_media_active |= IFM_1000_SX; break;
|
|
case BRGPHY_5708S_PG0_1000X_STAT1_SPEED_25G:
|
|
mii->mii_media_active |= IFM_2500_SX; break;
|
|
}
|
|
|
|
/* Check for MRBE auto-negotiated duplex results. */
|
|
if (xstat & BRGPHY_5708S_PG0_1000X_STAT1_FDX)
|
|
mii->mii_media_active |= IFM_FDX;
|
|
else
|
|
mii->mii_media_active |= IFM_HDX;
|
|
} else if (bsc->serdes_flags & BRGPHY_5709S) {
|
|
/* Select GP Status Block of the AN MMD, get autoneg results. */
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS);
|
|
xstat = PHY_READ(sc, BRGPHY_GP_STATUS_TOP_ANEG_STATUS);
|
|
|
|
/* Restore IEEE0 block (assumed in all brgphy(4) code). */
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
|
|
|
|
/* Check for MRBE auto-negotiated speed results. */
|
|
switch (xstat & BRGPHY_GP_STATUS_TOP_ANEG_SPEED_MASK) {
|
|
case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_10:
|
|
mii->mii_media_active |= IFM_10_FL; break;
|
|
case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_100:
|
|
mii->mii_media_active |= IFM_100_FX; break;
|
|
case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_1G:
|
|
mii->mii_media_active |= IFM_1000_SX; break;
|
|
case BRGPHY_GP_STATUS_TOP_ANEG_SPEED_25G:
|
|
mii->mii_media_active |= IFM_2500_SX; break;
|
|
}
|
|
|
|
/* Check for MRBE auto-negotiated duplex results. */
|
|
if (xstat & BRGPHY_GP_STATUS_TOP_ANEG_FDX)
|
|
mii->mii_media_active |= IFM_FDX;
|
|
else
|
|
mii->mii_media_active |= IFM_HDX;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
brgphy_mii_phy_auto(struct mii_softc *sc, int media)
|
|
{
|
|
int anar, ktcr = 0;
|
|
|
|
PHY_RESET(sc);
|
|
|
|
if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
|
|
anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
|
|
if ((media & IFM_FLOW) != 0 ||
|
|
(sc->mii_flags & MIIF_FORCEPAUSE) != 0)
|
|
anar |= BRGPHY_ANAR_PC | BRGPHY_ANAR_ASP;
|
|
PHY_WRITE(sc, BRGPHY_MII_ANAR, anar);
|
|
ktcr = BRGPHY_1000CTL_AFD | BRGPHY_1000CTL_AHD;
|
|
if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5701)
|
|
ktcr |= BRGPHY_1000CTL_MSE | BRGPHY_1000CTL_MSC;
|
|
PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
|
|
PHY_READ(sc, BRGPHY_MII_1000CTL);
|
|
} else {
|
|
anar = BRGPHY_SERDES_ANAR_FDX | BRGPHY_SERDES_ANAR_HDX;
|
|
if ((media & IFM_FLOW) != 0 ||
|
|
(sc->mii_flags & MIIF_FORCEPAUSE) != 0)
|
|
anar |= BRGPHY_SERDES_ANAR_BOTH_PAUSE;
|
|
PHY_WRITE(sc, BRGPHY_SERDES_ANAR, anar);
|
|
}
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_AUTOEN |
|
|
BRGPHY_BMCR_STARTNEG);
|
|
PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
|
|
}
|
|
|
|
/* Enable loopback to force the link down. */
|
|
static void
|
|
brgphy_enable_loopback(struct mii_softc *sc)
|
|
{
|
|
int i;
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
|
|
for (i = 0; i < 15000; i++) {
|
|
if (!(PHY_READ(sc, BRGPHY_MII_BMSR) & BRGPHY_BMSR_LINK))
|
|
break;
|
|
DELAY(10);
|
|
}
|
|
}
|
|
|
|
/* Turn off tap power management on 5401. */
|
|
static void
|
|
bcm5401_load_dspcode(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ BRGPHY_MII_AUXCTL, 0x0c20 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x1804 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x1204 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0132 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0232 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
DELAY(40);
|
|
}
|
|
|
|
static void
|
|
bcm5411_load_dspcode(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ 0x1c, 0x8c23 },
|
|
{ 0x1c, 0x8ca3 },
|
|
{ 0x1c, 0x8c23 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
void
|
|
bcm54k2_load_dspcode(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ 4, 0x01e1 },
|
|
{ 9, 0x0300 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
|
|
}
|
|
|
|
static void
|
|
brgphy_fixup_5704_a0_bug(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ 0x1c, 0x8d68 },
|
|
{ 0x1c, 0x8d68 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
static void
|
|
brgphy_fixup_adc_bug(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ BRGPHY_MII_AUXCTL, 0x0c00 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
static void
|
|
brgphy_fixup_adjust_trim(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ BRGPHY_MII_AUXCTL, 0x0c00 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x000a },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x110b },
|
|
{ BRGPHY_MII_TEST1, 0x0014 },
|
|
{ BRGPHY_MII_AUXCTL, 0x0400 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
static void
|
|
brgphy_fixup_ber_bug(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ BRGPHY_MII_AUXCTL, 0x0c00 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x000a },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x310b },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x201f },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x9506 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x401f },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
|
|
{ BRGPHY_MII_AUXCTL, 0x0400 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
static void
|
|
brgphy_fixup_crc_bug(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x0a75 },
|
|
{ 0x1c, 0x8c68 },
|
|
{ 0x1c, 0x8d68 },
|
|
{ 0x1c, 0x8c68 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
static void
|
|
brgphy_fixup_jitter_bug(struct mii_softc *sc)
|
|
{
|
|
static const struct {
|
|
int reg;
|
|
uint16_t val;
|
|
} dspcode[] = {
|
|
{ BRGPHY_MII_AUXCTL, 0x0c00 },
|
|
{ BRGPHY_MII_DSP_ADDR_REG, 0x000a },
|
|
{ BRGPHY_MII_DSP_RW_PORT, 0x010b },
|
|
{ BRGPHY_MII_AUXCTL, 0x0400 },
|
|
{ 0, 0 },
|
|
};
|
|
int i;
|
|
|
|
for (i = 0; dspcode[i].reg != 0; i++)
|
|
PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
|
|
}
|
|
|
|
static void
|
|
brgphy_fixup_disable_early_dac(struct mii_softc *sc)
|
|
{
|
|
uint32_t val;
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
|
|
val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
|
|
val &= ~(1 << 8);
|
|
PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);
|
|
|
|
}
|
|
|
|
static void
|
|
brgphy_ethernet_wirespeed(struct mii_softc *sc)
|
|
{
|
|
uint32_t val;
|
|
|
|
/* Enable Ethernet@WireSpeed. */
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
|
|
val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
|
|
}
|
|
|
|
static void
|
|
brgphy_bcm54xx_clock_delay(struct mii_softc *sc)
|
|
{
|
|
uint16_t val;
|
|
|
|
if (!(sc->mii_flags & (MIIF_RX_DELAY | MIIF_TX_DELAY)))
|
|
/* Adjusting the clocks in rgmii mode causes packet losses. */
|
|
return;
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_SHADOW_MISC |
|
|
BRGPHY_AUXCTL_SHADOW_MISC << BRGPHY_AUXCTL_MISC_READ_SHIFT);
|
|
val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
|
|
val &= BRGPHY_AUXCTL_MISC_DATA_MASK;
|
|
if (sc->mii_flags & MIIF_RX_DELAY)
|
|
val |= BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN;
|
|
else
|
|
val &= ~BRGPHY_AUXCTL_MISC_RGMII_SKEW_EN;
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, BRGPHY_AUXCTL_MISC_WRITE_EN |
|
|
BRGPHY_AUXCTL_SHADOW_MISC | val);
|
|
|
|
PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_CLK_CTRL);
|
|
val = PHY_READ(sc, BRGPHY_MII_SHADOW_1C);
|
|
val &= BRGPHY_SHADOW_1C_DATA_MASK;
|
|
if (sc->mii_flags & MIIF_TX_DELAY)
|
|
val |= BRGPHY_SHADOW_1C_GTXCLK_EN;
|
|
else
|
|
val &= ~BRGPHY_SHADOW_1C_GTXCLK_EN;
|
|
PHY_WRITE(sc, BRGPHY_MII_SHADOW_1C, BRGPHY_SHADOW_1C_WRITE_EN |
|
|
BRGPHY_SHADOW_1C_CLK_CTRL | val);
|
|
}
|
|
|
|
static void
|
|
brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
|
|
{
|
|
uint32_t val;
|
|
|
|
/* Set or clear jumbo frame settings in the PHY. */
|
|
if (mtu > ETHER_MAX_LEN) {
|
|
if (sc->mii_mpd_model == MII_MODEL_BROADCOM_BCM5401) {
|
|
/* BCM5401 PHY cannot read-modify-write. */
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
|
|
} else {
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
|
|
val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
|
|
val | BRGPHY_AUXCTL_LONG_PKT);
|
|
}
|
|
|
|
val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
|
|
val | BRGPHY_PHY_EXTCTL_HIGH_LA);
|
|
} else {
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
|
|
val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
|
|
val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
|
|
|
|
val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
|
|
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
|
|
val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
|
|
}
|
|
}
|
|
|
|
static void
|
|
brgphy_reset(struct mii_softc *sc)
|
|
{
|
|
struct bge_softc *bge_sc = NULL;
|
|
struct bce_softc *bce_sc = NULL;
|
|
if_t ifp;
|
|
int i, val;
|
|
|
|
/*
|
|
* Perform a reset. Note that at least some Broadcom PHYs default to
|
|
* being powered down as well as isolated after a reset but don't work
|
|
* if one or both of these bits are cleared. However, they just work
|
|
* fine if both bits remain set, so we don't use mii_phy_reset() here.
|
|
*/
|
|
PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
|
|
|
|
/* Wait 100ms for it to complete. */
|
|
for (i = 0; i < 100; i++) {
|
|
if ((PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_RESET) == 0)
|
|
break;
|
|
DELAY(1000);
|
|
}
|
|
|
|
/* Handle any PHY specific procedures following the reset. */
|
|
switch (sc->mii_mpd_oui) {
|
|
case MII_OUI_BROADCOM:
|
|
switch (sc->mii_mpd_model) {
|
|
case MII_MODEL_BROADCOM_BCM5400:
|
|
bcm5401_load_dspcode(sc);
|
|
break;
|
|
case MII_MODEL_BROADCOM_BCM5401:
|
|
if (sc->mii_mpd_rev == 1 || sc->mii_mpd_rev == 3)
|
|
bcm5401_load_dspcode(sc);
|
|
break;
|
|
case MII_MODEL_BROADCOM_BCM5411:
|
|
bcm5411_load_dspcode(sc);
|
|
break;
|
|
case MII_MODEL_BROADCOM_BCM54K2:
|
|
bcm54k2_load_dspcode(sc);
|
|
break;
|
|
}
|
|
break;
|
|
case MII_OUI_BROADCOM3:
|
|
switch (sc->mii_mpd_model) {
|
|
case MII_MODEL_BROADCOM3_BCM5717C:
|
|
case MII_MODEL_BROADCOM3_BCM5719C:
|
|
case MII_MODEL_BROADCOM3_BCM5720C:
|
|
case MII_MODEL_BROADCOM3_BCM57765:
|
|
return;
|
|
}
|
|
break;
|
|
case MII_OUI_BROADCOM4:
|
|
return;
|
|
}
|
|
|
|
ifp = sc->mii_pdata->mii_ifp;
|
|
|
|
/* Find the driver associated with this PHY. */
|
|
if (mii_phy_mac_match(sc, "bge"))
|
|
bge_sc = mii_phy_mac_softc(sc);
|
|
else if (mii_phy_mac_match(sc, "bce"))
|
|
bce_sc = mii_phy_mac_softc(sc);
|
|
|
|
if (bge_sc) {
|
|
/* Fix up various bugs */
|
|
if (bge_sc->bge_phy_flags & BGE_PHY_5704_A0_BUG)
|
|
brgphy_fixup_5704_a0_bug(sc);
|
|
if (bge_sc->bge_phy_flags & BGE_PHY_ADC_BUG)
|
|
brgphy_fixup_adc_bug(sc);
|
|
if (bge_sc->bge_phy_flags & BGE_PHY_ADJUST_TRIM)
|
|
brgphy_fixup_adjust_trim(sc);
|
|
if (bge_sc->bge_phy_flags & BGE_PHY_BER_BUG)
|
|
brgphy_fixup_ber_bug(sc);
|
|
if (bge_sc->bge_phy_flags & BGE_PHY_CRC_BUG)
|
|
brgphy_fixup_crc_bug(sc);
|
|
if (bge_sc->bge_phy_flags & BGE_PHY_JITTER_BUG)
|
|
brgphy_fixup_jitter_bug(sc);
|
|
|
|
if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
|
|
brgphy_jumbo_settings(sc, if_getmtu(ifp));
|
|
|
|
if ((bge_sc->bge_phy_flags & BGE_PHY_NO_WIRESPEED) == 0)
|
|
brgphy_ethernet_wirespeed(sc);
|
|
|
|
/* Enable Link LED on Dell boxes */
|
|
if (bge_sc->bge_phy_flags & BGE_PHY_NO_3LED) {
|
|
PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
|
|
PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
|
|
~BRGPHY_PHY_EXTCTL_3_LED);
|
|
}
|
|
|
|
/* Adjust output voltage (From Linux driver) */
|
|
if (bge_sc->bge_asicrev == BGE_ASICREV_BCM5906)
|
|
PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
|
|
} else if (bce_sc) {
|
|
if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5708 &&
|
|
(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
|
|
/* Store autoneg capabilities/results in digital block (Page 0) */
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG3_PG2);
|
|
PHY_WRITE(sc, BRGPHY_5708S_PG2_DIGCTL_3_0,
|
|
BRGPHY_5708S_PG2_DIGCTL_3_0_USE_IEEE);
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR, BRGPHY_5708S_DIG_PG0);
|
|
|
|
/* Enable fiber mode and autodetection */
|
|
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL1,
|
|
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL1) |
|
|
BRGPHY_5708S_PG0_1000X_CTL1_AUTODET_EN |
|
|
BRGPHY_5708S_PG0_1000X_CTL1_FIBER_MODE);
|
|
|
|
/* Enable parallel detection */
|
|
PHY_WRITE(sc, BRGPHY_5708S_PG0_1000X_CTL2,
|
|
PHY_READ(sc, BRGPHY_5708S_PG0_1000X_CTL2) |
|
|
BRGPHY_5708S_PG0_1000X_CTL2_PAR_DET_EN);
|
|
|
|
/* Advertise 2.5G support through next page during autoneg */
|
|
if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
|
|
PHY_WRITE(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1,
|
|
PHY_READ(sc, BRGPHY_5708S_ANEG_NXT_PG_XMIT1) |
|
|
BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G);
|
|
|
|
/* Increase TX signal amplitude */
|
|
if ((BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_A0) ||
|
|
(BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B0) ||
|
|
(BCE_CHIP_ID(bce_sc) == BCE_CHIP_ID_5708_B1)) {
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
|
BRGPHY_5708S_TX_MISC_PG5);
|
|
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL1,
|
|
PHY_READ(sc, BRGPHY_5708S_PG5_TXACTL1) & ~0x30);
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
|
BRGPHY_5708S_DIG_PG0);
|
|
}
|
|
|
|
/* Backplanes use special driver/pre-driver/pre-emphasis values. */
|
|
if ((bce_sc->bce_shared_hw_cfg & BCE_SHARED_HW_CFG_PHY_BACKPLANE) &&
|
|
(bce_sc->bce_port_hw_cfg & BCE_PORT_HW_CFG_CFG_TXCTL3_MASK)) {
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
|
BRGPHY_5708S_TX_MISC_PG5);
|
|
PHY_WRITE(sc, BRGPHY_5708S_PG5_TXACTL3,
|
|
bce_sc->bce_port_hw_cfg &
|
|
BCE_PORT_HW_CFG_CFG_TXCTL3_MASK);
|
|
PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
|
|
BRGPHY_5708S_DIG_PG0);
|
|
}
|
|
} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709 &&
|
|
(bce_sc->bce_phy_flags & BCE_PHY_SERDES_FLAG)) {
|
|
/* Select the SerDes Digital block of the AN MMD. */
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_SERDES_DIG);
|
|
val = PHY_READ(sc, BRGPHY_SERDES_DIG_1000X_CTL1);
|
|
val &= ~BRGPHY_SD_DIG_1000X_CTL1_AUTODET;
|
|
val |= BRGPHY_SD_DIG_1000X_CTL1_FIBER;
|
|
PHY_WRITE(sc, BRGPHY_SERDES_DIG_1000X_CTL1, val);
|
|
|
|
/* Select the Over 1G block of the AN MMD. */
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_OVER_1G);
|
|
|
|
/* Enable autoneg "Next Page" to advertise 2.5G support. */
|
|
val = PHY_READ(sc, BRGPHY_OVER_1G_UNFORMAT_PG1);
|
|
if (bce_sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
|
|
val |= BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
|
|
else
|
|
val &= ~BRGPHY_5708S_ANEG_NXT_PG_XMIT1_25G;
|
|
PHY_WRITE(sc, BRGPHY_OVER_1G_UNFORMAT_PG1, val);
|
|
|
|
/* Select the Multi-Rate Backplane Ethernet block of the AN MMD. */
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_MRBE);
|
|
|
|
/* Enable MRBE speed autoneg. */
|
|
val = PHY_READ(sc, BRGPHY_MRBE_MSG_PG5_NP);
|
|
val |= BRGPHY_MRBE_MSG_PG5_NP_MBRE |
|
|
BRGPHY_MRBE_MSG_PG5_NP_T2;
|
|
PHY_WRITE(sc, BRGPHY_MRBE_MSG_PG5_NP, val);
|
|
|
|
/* Select the Clause 73 User B0 block of the AN MMD. */
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_CL73_USER_B0);
|
|
|
|
/* Enable MRBE speed autoneg. */
|
|
PHY_WRITE(sc, BRGPHY_CL73_USER_B0_MBRE_CTL1,
|
|
BRGPHY_CL73_USER_B0_MBRE_CTL1_NP_AFT_BP |
|
|
BRGPHY_CL73_USER_B0_MBRE_CTL1_STA_MGR |
|
|
BRGPHY_CL73_USER_B0_MBRE_CTL1_ANEG);
|
|
|
|
/* Restore IEEE0 block (assumed in all brgphy(4) code). */
|
|
PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
|
|
} else if (BCE_CHIP_NUM(bce_sc) == BCE_CHIP_NUM_5709) {
|
|
if ((BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Ax) ||
|
|
(BCE_CHIP_REV(bce_sc) == BCE_CHIP_REV_Bx))
|
|
brgphy_fixup_disable_early_dac(sc);
|
|
|
|
brgphy_jumbo_settings(sc, if_getmtu(ifp));
|
|
brgphy_ethernet_wirespeed(sc);
|
|
} else {
|
|
brgphy_fixup_ber_bug(sc);
|
|
brgphy_jumbo_settings(sc, if_getmtu(ifp));
|
|
brgphy_ethernet_wirespeed(sc);
|
|
}
|
|
}
|
|
}
|