359 lines
9.8 KiB
C
359 lines
9.8 KiB
C
/*-
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* Copyright (C) 2012-2016 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/buf.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include "nvme_private.h"
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static int nvme_pci_probe(device_t);
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static int nvme_pci_attach(device_t);
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static int nvme_pci_detach(device_t);
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static int nvme_pci_suspend(device_t);
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static int nvme_pci_resume(device_t);
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static int nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr);
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static device_method_t nvme_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, nvme_pci_probe),
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DEVMETHOD(device_attach, nvme_pci_attach),
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DEVMETHOD(device_detach, nvme_pci_detach),
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DEVMETHOD(device_suspend, nvme_pci_suspend),
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DEVMETHOD(device_resume, nvme_pci_resume),
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DEVMETHOD(device_shutdown, nvme_shutdown),
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{ 0, 0 }
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};
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static driver_t nvme_pci_driver = {
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"nvme",
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nvme_pci_methods,
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sizeof(struct nvme_controller),
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};
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DRIVER_MODULE(nvme, pci, nvme_pci_driver, NULL, NULL);
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static struct _pcsid
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{
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uint32_t devid;
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int match_subdevice;
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uint16_t subdevice;
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const char *desc;
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uint32_t quirks;
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} pci_ids[] = {
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{ 0x01118086, 0, 0, "NVMe Controller" },
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{ IDT32_PCI_ID, 0, 0, "IDT NVMe Controller (32 channel)" },
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{ IDT8_PCI_ID, 0, 0, "IDT NVMe Controller (8 channel)" },
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{ 0x09538086, 1, 0x3702, "DC P3700 SSD" },
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{ 0x09538086, 1, 0x3703, "DC P3700 SSD [2.5\" SFF]" },
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{ 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" },
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{ 0x09538086, 1, 0x3705, "DC P3500 SSD [2.5\" SFF]" },
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{ 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" },
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{ 0x09538086, 1, 0x370a, "DC P3600 SSD [2.5\" SFF]" },
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{ 0x09538086, 0, 0, "Intel DC PC3500", QUIRK_INTEL_ALIGNMENT },
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{ 0x0a538086, 0, 0, "Intel DC PC3520", QUIRK_INTEL_ALIGNMENT },
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{ 0x0a548086, 0, 0, "Intel DC PC4500", QUIRK_INTEL_ALIGNMENT },
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{ 0x0a558086, 0, 0, "Dell Intel P4600", QUIRK_INTEL_ALIGNMENT },
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{ 0x00031c58, 0, 0, "HGST SN100", QUIRK_DELAY_B4_CHK_RDY },
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{ 0x00231c58, 0, 0, "WDC SN200", QUIRK_DELAY_B4_CHK_RDY },
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{ 0x05401c5f, 0, 0, "Memblaze Pblaze4", QUIRK_DELAY_B4_CHK_RDY },
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{ 0xa821144d, 0, 0, "Samsung PM1725", QUIRK_DELAY_B4_CHK_RDY },
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{ 0xa822144d, 0, 0, "Samsung PM1725a", QUIRK_DELAY_B4_CHK_RDY },
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{ 0x07f015ad, 0, 0, "VMware NVMe Controller" },
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{ 0x2003106b, 0, 0, "Apple S3X NVMe Controller" },
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{ 0x00000000, 0, 0, NULL }
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};
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static int
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nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep)
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{
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if (devid != ep->devid)
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return 0;
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if (!ep->match_subdevice)
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return 1;
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if (subdevice == ep->subdevice)
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return 1;
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else
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return 0;
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}
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static int
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nvme_pci_probe (device_t device)
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{
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struct nvme_controller *ctrlr = DEVICE2SOFTC(device);
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struct _pcsid *ep;
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uint32_t devid;
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uint16_t subdevice;
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devid = pci_get_devid(device);
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subdevice = pci_get_subdevice(device);
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ep = pci_ids;
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while (ep->devid) {
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if (nvme_match(devid, subdevice, ep))
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break;
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++ep;
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}
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if (ep->devid)
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ctrlr->quirks = ep->quirks;
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if (ep->desc) {
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device_set_desc(device, ep->desc);
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return (BUS_PROBE_DEFAULT);
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}
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#if defined(PCIS_STORAGE_NVM)
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if (pci_get_class(device) == PCIC_STORAGE &&
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pci_get_subclass(device) == PCIS_STORAGE_NVM &&
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pci_get_progif(device) == PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) {
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device_set_desc(device, "Generic NVMe Device");
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return (BUS_PROBE_GENERIC);
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}
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#endif
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return (ENXIO);
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}
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static int
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nvme_ctrlr_allocate_bar(struct nvme_controller *ctrlr)
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{
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ctrlr->resource_id = PCIR_BAR(0);
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ctrlr->resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY,
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&ctrlr->resource_id, RF_ACTIVE);
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if(ctrlr->resource == NULL) {
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nvme_printf(ctrlr, "unable to allocate pci resource\n");
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return (ENOMEM);
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}
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ctrlr->bus_tag = rman_get_bustag(ctrlr->resource);
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ctrlr->bus_handle = rman_get_bushandle(ctrlr->resource);
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ctrlr->regs = (struct nvme_registers *)ctrlr->bus_handle;
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/*
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* The NVMe spec allows for the MSI-X table to be placed behind
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* BAR 4/5, separate from the control/doorbell registers. Always
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* try to map this bar, because it must be mapped prior to calling
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* pci_alloc_msix(). If the table isn't behind BAR 4/5,
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* bus_alloc_resource() will just return NULL which is OK.
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*/
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ctrlr->bar4_resource_id = PCIR_BAR(4);
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ctrlr->bar4_resource = bus_alloc_resource_any(ctrlr->dev, SYS_RES_MEMORY,
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&ctrlr->bar4_resource_id, RF_ACTIVE);
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return (0);
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}
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static int
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nvme_pci_attach(device_t dev)
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{
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struct nvme_controller*ctrlr = DEVICE2SOFTC(dev);
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int status;
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ctrlr->dev = dev;
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status = nvme_ctrlr_allocate_bar(ctrlr);
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if (status != 0)
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goto bad;
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pci_enable_busmaster(dev);
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status = nvme_ctrlr_setup_interrupts(ctrlr);
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if (status != 0)
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goto bad;
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return nvme_attach(dev);
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bad:
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if (ctrlr->resource != NULL) {
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bus_release_resource(dev, SYS_RES_MEMORY,
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ctrlr->resource_id, ctrlr->resource);
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}
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if (ctrlr->bar4_resource != NULL) {
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bus_release_resource(dev, SYS_RES_MEMORY,
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ctrlr->bar4_resource_id, ctrlr->bar4_resource);
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}
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if (ctrlr->tag)
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bus_teardown_intr(dev, ctrlr->res, ctrlr->tag);
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if (ctrlr->res)
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bus_release_resource(dev, SYS_RES_IRQ,
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rman_get_rid(ctrlr->res), ctrlr->res);
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if (ctrlr->msi_count > 0)
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pci_release_msi(dev);
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return status;
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}
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static int
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nvme_pci_detach(device_t dev)
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{
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struct nvme_controller*ctrlr = DEVICE2SOFTC(dev);
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int rv;
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rv = nvme_detach(dev);
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if (ctrlr->msi_count > 0)
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pci_release_msi(dev);
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pci_disable_busmaster(dev);
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return (rv);
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}
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static int
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nvme_ctrlr_setup_shared(struct nvme_controller *ctrlr, int rid)
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{
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int error;
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ctrlr->num_io_queues = 1;
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ctrlr->rid = rid;
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ctrlr->res = bus_alloc_resource_any(ctrlr->dev, SYS_RES_IRQ,
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&ctrlr->rid, RF_SHAREABLE | RF_ACTIVE);
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if (ctrlr->res == NULL) {
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nvme_printf(ctrlr, "unable to allocate shared interrupt\n");
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return (ENOMEM);
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}
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error = bus_setup_intr(ctrlr->dev, ctrlr->res,
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INTR_TYPE_MISC | INTR_MPSAFE, NULL, nvme_ctrlr_shared_handler,
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ctrlr, &ctrlr->tag);
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if (error) {
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nvme_printf(ctrlr, "unable to setup shared interrupt\n");
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return (error);
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}
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return (0);
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}
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static int
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nvme_ctrlr_setup_interrupts(struct nvme_controller *ctrlr)
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{
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device_t dev;
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int force_intx, num_io_queues, per_cpu_io_queues;
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int min_cpus_per_ioq;
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int num_vectors_requested;
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dev = ctrlr->dev;
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force_intx = 0;
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TUNABLE_INT_FETCH("hw.nvme.force_intx", &force_intx);
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if (force_intx)
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return (nvme_ctrlr_setup_shared(ctrlr, 0));
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if (pci_msix_count(dev) == 0)
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goto msi;
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/*
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* Try to allocate one MSI-X per core for I/O queues, plus one
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* for admin queue, but accept single shared MSI-X if have to.
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* Fall back to MSI if can't get any MSI-X.
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*/
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num_io_queues = mp_ncpus;
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TUNABLE_INT_FETCH("hw.nvme.num_io_queues", &num_io_queues);
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if (num_io_queues < 1 || num_io_queues > mp_ncpus)
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num_io_queues = mp_ncpus;
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per_cpu_io_queues = 1;
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TUNABLE_INT_FETCH("hw.nvme.per_cpu_io_queues", &per_cpu_io_queues);
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if (per_cpu_io_queues == 0)
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num_io_queues = 1;
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min_cpus_per_ioq = smp_threads_per_core;
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TUNABLE_INT_FETCH("hw.nvme.min_cpus_per_ioq", &min_cpus_per_ioq);
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if (min_cpus_per_ioq > 1) {
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num_io_queues = min(num_io_queues,
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max(1, mp_ncpus / min_cpus_per_ioq));
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}
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num_io_queues = min(num_io_queues, max(1, pci_msix_count(dev) - 1));
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again:
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if (num_io_queues > vm_ndomains)
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num_io_queues -= num_io_queues % vm_ndomains;
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num_vectors_requested = min(num_io_queues + 1, pci_msix_count(dev));
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ctrlr->msi_count = num_vectors_requested;
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if (pci_alloc_msix(dev, &ctrlr->msi_count) != 0) {
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nvme_printf(ctrlr, "unable to allocate MSI-X\n");
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ctrlr->msi_count = 0;
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goto msi;
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}
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if (ctrlr->msi_count == 1)
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return (nvme_ctrlr_setup_shared(ctrlr, 1));
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if (ctrlr->msi_count != num_vectors_requested) {
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pci_release_msi(dev);
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num_io_queues = ctrlr->msi_count - 1;
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goto again;
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}
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ctrlr->num_io_queues = num_io_queues;
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return (0);
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msi:
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/*
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* Try to allocate 2 MSIs (admin and I/O queues), but accept single
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* shared if have to. Fall back to INTx if can't get any MSI.
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*/
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ctrlr->msi_count = min(pci_msi_count(dev), 2);
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if (ctrlr->msi_count > 0) {
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if (pci_alloc_msi(dev, &ctrlr->msi_count) != 0) {
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nvme_printf(ctrlr, "unable to allocate MSI\n");
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ctrlr->msi_count = 0;
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} else if (ctrlr->msi_count == 2) {
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ctrlr->num_io_queues = 1;
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return (0);
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}
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}
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return (nvme_ctrlr_setup_shared(ctrlr, ctrlr->msi_count > 0 ? 1 : 0));
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}
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static int
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nvme_pci_suspend(device_t dev)
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{
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struct nvme_controller *ctrlr;
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ctrlr = DEVICE2SOFTC(dev);
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return (nvme_ctrlr_suspend(ctrlr));
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}
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static int
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nvme_pci_resume(device_t dev)
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{
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struct nvme_controller *ctrlr;
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ctrlr = DEVICE2SOFTC(dev);
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return (nvme_ctrlr_resume(ctrlr));
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}
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