179 lines
5.8 KiB
C
179 lines
5.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* Driver for Qualcomm IPQ4018 clock and reset device */
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/sglist.h>
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#include <sys/random.h>
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#include <sys/stdatomic.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "hwreset_if.h"
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#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
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#include "qcom_gcc_ipq4018_var.h"
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static const struct qcom_gcc_ipq4018_reset_entry gcc_ipq4019_reset_list[] = {
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[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
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[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
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[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
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[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
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[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
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[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
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[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
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[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
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[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
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[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
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[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
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[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
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[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
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[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
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[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
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[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
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[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
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[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
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[PCIE_AHB_ARES] = { 0x1d010, 10 },
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[PCIE_PWR_ARES] = { 0x1d010, 9 },
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[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
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[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
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[PCIE_PHY_ARES] = { 0x1d010, 6 },
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[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
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[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
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[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
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[PCIE_PIPE_ARES] = { 0x1d010, 2 },
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[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
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[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
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[ESS_RESET] = { 0x12008, 0},
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[GCC_BLSP1_BCR] = {0x01000, 0},
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[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
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[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
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[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
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[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
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[GCC_BIMC_BCR] = {0x04000, 0},
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[GCC_TLMM_BCR] = {0x05000, 0},
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[GCC_IMEM_BCR] = {0x0E000, 0},
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[GCC_ESS_BCR] = {0x12008, 0},
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[GCC_PRNG_BCR] = {0x13000, 0},
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[GCC_BOOT_ROM_BCR] = {0x13008, 0},
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[GCC_CRYPTO_BCR] = {0x16000, 0},
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[GCC_SDCC1_BCR] = {0x18000, 0},
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[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
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[GCC_AUDIO_BCR] = {0x1B008, 0},
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[GCC_QPIC_BCR] = {0x1C000, 0},
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[GCC_PCIE_BCR] = {0x1D000, 0},
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[GCC_USB2_BCR] = {0x1E008, 0},
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[GCC_USB2_PHY_BCR] = {0x1E018, 0},
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[GCC_USB3_BCR] = {0x1E024, 0},
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[GCC_USB3_PHY_BCR] = {0x1E034, 0},
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[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
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[GCC_PCNOC_BCR] = {0x2102C, 0},
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[GCC_DCD_BCR] = {0x21038, 0},
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[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
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[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
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[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
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[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
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[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
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[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
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[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
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[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
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[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
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[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
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[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
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[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
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[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
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[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
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[GCC_TCSR_BCR] = {0x22000, 0},
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[GCC_MPM_BCR] = {0x24000, 0},
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[GCC_SPDM_BCR] = {0x25000, 0},
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};
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int
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qcom_gcc_ipq4018_hwreset_assert(device_t dev, intptr_t id, bool reset)
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{
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struct qcom_gcc_ipq4018_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (id > nitems(gcc_ipq4019_reset_list)) {
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device_printf(dev, "%s: invalid id (%d)\n", __func__, id);
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return (EINVAL);
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}
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mtx_lock(&sc->mtx);
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reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);
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if (reset)
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reg |= (1U << gcc_ipq4019_reset_list[id].bit);
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else
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reg &= ~(1U << gcc_ipq4019_reset_list[id].bit);
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bus_write_4(sc->reg, gcc_ipq4019_reset_list[id].reg, reg);
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mtx_unlock(&sc->mtx);
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return (0);
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}
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int
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qcom_gcc_ipq4018_hwreset_is_asserted(device_t dev, intptr_t id, bool *reset)
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{
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struct qcom_gcc_ipq4018_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (id > nitems(gcc_ipq4019_reset_list)) {
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device_printf(dev, "%s: invalid id (%d)\n", __func__, id);
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return (EINVAL);
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}
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mtx_lock(&sc->mtx);
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reg = bus_read_4(sc->reg, gcc_ipq4019_reset_list[id].reg);
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if (reg & ((1U << gcc_ipq4019_reset_list[id].bit)))
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*reset = true;
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else
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*reset = false;
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mtx_unlock(&sc->mtx);
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device_printf(dev, "called; id=%d\n", id);
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return (0);
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}
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