907 lines
23 KiB
C
907 lines
23 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/gpio.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_extern.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/fdt/fdt_pinctrl.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include "spibus_if.h"
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#include <dev/qcom_qup/qcom_spi_var.h>
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#include <dev/qcom_qup/qcom_qup_reg.h>
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#include <dev/qcom_qup/qcom_spi_reg.h>
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#include <dev/qcom_qup/qcom_spi_debug.h>
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static struct ofw_compat_data compat_data[] = {
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{ "qcom,spi-qup-v1.1.1", QCOM_SPI_HW_QPI_V1_1 },
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{ "qcom,spi-qup-v2.1.1", QCOM_SPI_HW_QPI_V2_1 },
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{ "qcom,spi-qup-v2.2.1", QCOM_SPI_HW_QPI_V2_2 },
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{ NULL, 0 }
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};
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/*
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* Flip the CS GPIO line either active or inactive.
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*
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* Actually listen to the CS polarity.
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*/
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static void
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qcom_spi_set_chipsel(struct qcom_spi_softc *sc, int cs, bool active)
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{
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bool pinactive;
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bool invert = !! (cs & SPIBUS_CS_HIGH);
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cs = cs & ~SPIBUS_CS_HIGH;
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if (sc->cs_pins[cs] == NULL) {
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device_printf(sc->sc_dev,
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"%s: cs=%u, active=%u, invert=%u, no gpio?\n",
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__func__, cs, active, invert);
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return;
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}
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QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_CHIPSELECT,
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"%s: cs=%u active=%u\n", __func__, cs, active);
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/*
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* Default rule here is CS is active low.
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*/
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if (active)
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pinactive = false;
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else
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pinactive = true;
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/*
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* Invert the CS line if required.
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*/
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if (invert)
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pinactive = !! pinactive;
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gpio_pin_set_active(sc->cs_pins[cs], pinactive);
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gpio_pin_is_active(sc->cs_pins[cs], &pinactive);
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}
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static void
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qcom_spi_intr(void *arg)
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{
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struct qcom_spi_softc *sc = arg;
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int ret;
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QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR, "%s: called\n", __func__);
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QCOM_SPI_LOCK(sc);
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ret = qcom_spi_hw_interrupt_handle(sc);
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if (ret != 0) {
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device_printf(sc->sc_dev,
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"ERROR: failed to read intr status\n");
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goto done;
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}
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/*
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* Handle spurious interrupts outside of an actual
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* transfer.
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*/
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if (sc->transfer.active == false) {
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device_printf(sc->sc_dev,
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"ERROR: spurious interrupt\n");
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qcom_spi_hw_ack_opmode(sc);
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goto done;
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}
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/* Now, handle interrupts */
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if (sc->intr.error) {
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sc->intr.error = false;
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device_printf(sc->sc_dev, "ERROR: intr\n");
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}
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if (sc->intr.do_rx) {
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sc->intr.do_rx = false;
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QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR,
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"%s: PIO_READ\n", __func__);
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if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO)
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ret = qcom_spi_hw_read_pio_fifo(sc);
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else
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ret = qcom_spi_hw_read_pio_block(sc);
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if (ret != 0) {
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device_printf(sc->sc_dev,
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"ERROR: qcom_spi_hw_read failed (%u)\n", ret);
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goto done;
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}
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}
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if (sc->intr.do_tx) {
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sc->intr.do_tx = false;
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QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR,
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"%s: PIO_WRITE\n", __func__);
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/*
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* For FIFO operations we do not do a write here, we did
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* it at the beginning of the transfer.
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*
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* For BLOCK operations yes, we call the routine.
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*/
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if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO)
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ret = qcom_spi_hw_ack_write_pio_fifo(sc);
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else
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ret = qcom_spi_hw_write_pio_block(sc);
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if (ret != 0) {
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device_printf(sc->sc_dev,
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"ERROR: qcom_spi_hw_write failed (%u)\n", ret);
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goto done;
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}
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}
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/*
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* Do this last. We may actually have completed the
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* transfer in the PIO receive path above and it will
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* set the done flag here.
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*/
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if (sc->intr.done) {
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sc->intr.done = false;
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sc->transfer.done = true;
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QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR,
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"%s: transfer done\n", __func__);
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wakeup(sc);
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}
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done:
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QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_INTR,
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"%s: done\n", __func__);
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QCOM_SPI_UNLOCK(sc);
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}
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static int
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qcom_spi_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "Qualcomm SPI Interface");
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return (BUS_PROBE_DEFAULT);
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}
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/*
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* Allocate GPIOs if provided in the SPI controller block.
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*
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* Some devices will use GPIO lines for chip select.
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* It's also quite annoying because some devices will want to use
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* the hardware provided CS gating for say, the first chipselect block,
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* and then use GPIOs for the later ones.
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*
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* So here we just assume for now that SPI index 0 uses the hardware
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* lines, and >0 use GPIO lines. Revisit this if better hardware
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* shows up.
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*
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* And finally, iterating over the cs-gpios list to allocate GPIOs
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* doesn't actually tell us what the polarity is. For that we need
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* to actually iterate over the list of child nodes and check what
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* their properties are (and look for "spi-cs-high".)
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*/
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static void
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qcom_spi_attach_gpios(struct qcom_spi_softc *sc)
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{
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phandle_t node;
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int idx, err;
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/* Allocate gpio pins for configured chip selects. */
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node = ofw_bus_get_node(sc->sc_dev);
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for (idx = 0; idx < nitems(sc->cs_pins); idx++) {
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err = gpio_pin_get_by_ofw_propidx(sc->sc_dev, node,
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"cs-gpios", idx, &sc->cs_pins[idx]);
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if (err == 0) {
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err = gpio_pin_setflags(sc->cs_pins[idx],
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GPIO_PIN_OUTPUT);
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if (err != 0) {
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device_printf(sc->sc_dev,
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"error configuring gpio for"
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" cs %u (%d)\n", idx, err);
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}
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/*
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* We can't set this HIGH right now because
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* we don't know if it needs to be set to
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* high for inactive or low for inactive
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* based on the child SPI device flags.
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*/
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#if 0
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gpio_pin_set_active(sc->cs_pins[idx], 1);
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gpio_pin_is_active(sc->cs_pins[idx], &tmp);
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#endif
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} else {
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device_printf(sc->sc_dev,
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"cannot configure gpio for chip select %u\n", idx);
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sc->cs_pins[idx] = NULL;
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}
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}
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}
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static void
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qcom_spi_sysctl_attach(struct qcom_spi_softc *sc)
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{
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struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
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struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
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SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
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"debug", CTLFLAG_RW, &sc->sc_debug, 0,
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"control debugging printfs");
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}
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static int
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qcom_spi_attach(device_t dev)
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{
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struct qcom_spi_softc *sc = device_get_softc(dev);
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int rid, ret, i, val;
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sc->sc_dev = dev;
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/*
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* Hardware version is stored in the ofw_compat_data table.
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*/
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sc->hw_version =
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ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "ERROR: Could not map memory\n");
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ret = ENXIO;
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goto error;
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}
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (!sc->sc_irq_res) {
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device_printf(dev, "ERROR: Could not map interrupt\n");
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ret = ENXIO;
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goto error;
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}
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ret = bus_setup_intr(dev, sc->sc_irq_res,
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INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, qcom_spi_intr, sc, &sc->sc_irq_h);
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if (ret != 0) {
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device_printf(dev, "ERROR: could not configure interrupt "
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"(%d)\n",
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ret);
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goto error;
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}
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qcom_spi_attach_gpios(sc);
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ret = clk_get_by_ofw_name(dev, 0, "core", &sc->clk_core);
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if (ret != 0) {
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device_printf(dev, "ERROR: could not get %s clock (%d)\n",
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"core", ret);
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goto error;
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}
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ret = clk_get_by_ofw_name(dev, 0, "iface", &sc->clk_iface);
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if (ret != 0) {
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device_printf(dev, "ERROR: could not get %s clock (%d)\n",
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"iface", ret);
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goto error;
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}
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/* Bring up initial clocks if they're off */
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ret = clk_enable(sc->clk_core);
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if (ret != 0) {
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device_printf(dev, "ERROR: couldn't enable core clock (%u)\n",
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ret);
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goto error;
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}
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ret = clk_enable(sc->clk_iface);
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if (ret != 0) {
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device_printf(dev, "ERROR: couldn't enable iface clock (%u)\n",
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ret);
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goto error;
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}
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/*
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* Read optional spi-max-frequency
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*/
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if (OF_getencprop(ofw_bus_get_node(dev), "spi-max-frequency",
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&val, sizeof(val)) > 0)
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sc->config.max_frequency = val;
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else
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sc->config.max_frequency = SPI_MAX_RATE;
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/*
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* Read optional cs-select
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*/
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if (OF_getencprop(ofw_bus_get_node(dev), "cs-select",
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&val, sizeof(val)) > 0)
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sc->config.cs_select = val;
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else
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sc->config.cs_select = 0;
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/*
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* Read optional num-cs
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*/
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if (OF_getencprop(ofw_bus_get_node(dev), "num-cs",
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&val, sizeof(val)) > 0)
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sc->config.num_cs = val;
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else
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sc->config.num_cs = SPI_NUM_CHIPSELECTS;
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ret = fdt_pinctrl_configure_by_name(dev, "default");
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if (ret != 0) {
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device_printf(dev,
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"ERROR: could not configure default pinmux\n");
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goto error;
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}
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ret = qcom_spi_hw_read_controller_transfer_sizes(sc);
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if (ret != 0) {
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device_printf(dev, "ERROR: Could not read transfer config\n");
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goto error;
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}
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device_printf(dev, "BLOCK: input=%u bytes, output=%u bytes\n",
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sc->config.input_block_size,
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sc->config.output_block_size);
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device_printf(dev, "FIFO: input=%u bytes, output=%u bytes\n",
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sc->config.input_fifo_size,
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sc->config.output_fifo_size);
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/* QUP config */
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QCOM_SPI_LOCK(sc);
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ret = qcom_spi_hw_qup_init_locked(sc);
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if (ret != 0) {
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device_printf(dev, "ERROR: QUP init failed (%d)\n", ret);
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QCOM_SPI_UNLOCK(sc);
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goto error;
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}
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/* Initial SPI config */
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ret = qcom_spi_hw_spi_init_locked(sc);
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if (ret != 0) {
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device_printf(dev, "ERROR: SPI init failed (%d)\n", ret);
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QCOM_SPI_UNLOCK(sc);
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goto error;
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}
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QCOM_SPI_UNLOCK(sc);
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sc->spibus = device_add_child(dev, "spibus", -1);
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/* We're done, so shut down the interface clock for now */
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device_printf(dev, "DONE: shutting down interface clock for now\n");
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clk_disable(sc->clk_iface);
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/* Register for debug sysctl */
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qcom_spi_sysctl_attach(sc);
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return (bus_generic_attach(dev));
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error:
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if (sc->sc_irq_h)
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bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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if (sc->sc_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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if (sc->clk_core) {
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clk_disable(sc->clk_core);
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clk_release(sc->clk_core);
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}
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if (sc->clk_iface) {
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clk_disable(sc->clk_iface);
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clk_release(sc->clk_iface);
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}
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for (i = 0; i < CS_MAX; i++) {
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if (sc->cs_pins[i] != NULL)
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gpio_pin_release(sc->cs_pins[i]);
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}
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mtx_destroy(&sc->sc_mtx);
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return (ret);
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}
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/*
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* Do a PIO transfer.
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*
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* Note that right now the TX/RX lens need to match, I'm not doing
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* dummy reads / dummy writes as required if they're not the same
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* size. The QUP hardware supports doing multi-phase transactions
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* where the FIFO isn't engaged for transmit or receive, but it's
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* not yet being done here.
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*/
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static int
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qcom_spi_transfer_pio_block(struct qcom_spi_softc *sc, int mode,
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char *tx_buf, int tx_len, char *rx_buf, int rx_len)
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{
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int ret = 0;
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QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER, "%s: start\n",
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__func__);
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if (rx_len != tx_len) {
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device_printf(sc->sc_dev,
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"ERROR: tx/rx len doesn't match (%d/%d)\n",
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tx_len, rx_len);
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return (ENXIO);
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}
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QCOM_SPI_ASSERT_LOCKED(sc);
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/*
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* Make initial choices for transfer configuration.
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*/
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ret = qcom_spi_hw_setup_transfer_selection(sc, tx_len);
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if (ret != 0) {
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device_printf(sc->sc_dev,
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"ERROR: failed to setup transfer selection (%d)\n",
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ret);
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return (ret);
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}
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/* Now set suitable buffer/lengths */
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sc->transfer.tx_buf = tx_buf;
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sc->transfer.tx_len = tx_len;
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sc->transfer.rx_buf = rx_buf;
|
|
sc->transfer.rx_len = rx_len;
|
|
sc->transfer.done = false;
|
|
sc->transfer.active = false;
|
|
|
|
/*
|
|
* Loop until the full transfer set is done.
|
|
*
|
|
* qcom_spi_hw_setup_current_transfer() will take care of
|
|
* setting a maximum transfer size for the hardware and choose
|
|
* a suitable operating mode.
|
|
*/
|
|
while (sc->transfer.tx_offset < sc->transfer.tx_len) {
|
|
/*
|
|
* Set transfer to false early; this covers
|
|
* it also finishing a sub-transfer and we're
|
|
* about the put the block into RESET state before
|
|
* starting a new transfer.
|
|
*/
|
|
sc->transfer.active = false;
|
|
|
|
QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER,
|
|
"%s: tx=%d of %d bytes, rx=%d of %d bytes\n",
|
|
__func__,
|
|
sc->transfer.tx_offset, sc->transfer.tx_len,
|
|
sc->transfer.rx_offset, sc->transfer.rx_len);
|
|
|
|
/*
|
|
* Set state to RESET before doing anything.
|
|
*
|
|
* Otherwise the second sub-transfer that we queue up
|
|
* will generate interrupts immediately when we start
|
|
* configuring it here and it'll start underflowing.
|
|
*/
|
|
ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: can't transition to RESET (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
/* blank interrupt state; we'll do a RESET below */
|
|
bzero(&sc->intr, sizeof(sc->intr));
|
|
sc->transfer.done = false;
|
|
|
|
/*
|
|
* Configure what the transfer configuration for this
|
|
* sub-transfer will be.
|
|
*/
|
|
ret = qcom_spi_hw_setup_current_transfer(sc);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: failed to setup sub transfer (%d)\n",
|
|
ret);
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* For now since we're configuring up PIO, we only setup
|
|
* the PIO transfer size.
|
|
*/
|
|
ret = qcom_spi_hw_setup_pio_transfer_cnt(sc);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: qcom_spi_hw_setup_pio_transfer_cnt failed"
|
|
" (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
#if 0
|
|
/*
|
|
* This is what we'd do to setup the block transfer sizes.
|
|
*/
|
|
ret = qcom_spi_hw_setup_block_transfer_cnt(sc);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: qcom_spi_hw_setup_block_transfer_cnt failed"
|
|
" (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
#endif
|
|
|
|
ret = qcom_spi_hw_setup_io_modes(sc);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: qcom_spi_hw_setup_io_modes failed"
|
|
" (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
ret = qcom_spi_hw_setup_spi_io_clock_polarity(sc,
|
|
!! (mode & SPIBUS_MODE_CPOL));
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: qcom_spi_hw_setup_spi_io_clock_polarity"
|
|
" failed (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
ret = qcom_spi_hw_setup_spi_config(sc, sc->state.frequency,
|
|
!! (mode & SPIBUS_MODE_CPHA));
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: qcom_spi_hw_setup_spi_config failed"
|
|
" (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
ret = qcom_spi_hw_setup_qup_config(sc, !! (tx_len > 0),
|
|
!! (rx_len > 0));
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: qcom_spi_hw_setup_qup_config failed"
|
|
" (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
ret = qcom_spi_hw_setup_operational_mask(sc);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: qcom_spi_hw_setup_operational_mask failed"
|
|
" (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* Setup is done; reset the controller and start the PIO
|
|
* write.
|
|
*/
|
|
|
|
/*
|
|
* Set state to RUN; we may start getting interrupts that
|
|
* are valid and we need to handle.
|
|
*/
|
|
sc->transfer.active = true;
|
|
ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RUN);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: can't transition to RUN (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* Set state to PAUSE
|
|
*/
|
|
ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_PAUSE);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: can't transition to PAUSE (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* If FIFO mode, write data now. Else, we'll get an
|
|
* interrupt when it's time to populate more data
|
|
* in BLOCK mode.
|
|
*/
|
|
if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO)
|
|
ret = qcom_spi_hw_write_pio_fifo(sc);
|
|
else
|
|
ret = qcom_spi_hw_write_pio_block(sc);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: qcom_spi_hw_write failed (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* Set state to RUN
|
|
*/
|
|
ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RUN);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: can't transition to RUN (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* Wait for an interrupt notification (which will
|
|
* continue to drive the state machine for this
|
|
* sub-transfer) or timeout.
|
|
*/
|
|
ret = 0;
|
|
while (ret == 0 && sc->transfer.done == false) {
|
|
QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER,
|
|
"%s: waiting\n", __func__);
|
|
ret = msleep(sc, &sc->sc_mtx, 0, "qcom_spi", 0);
|
|
}
|
|
}
|
|
done:
|
|
/*
|
|
* Complete; put controller into reset.
|
|
*
|
|
* Don't worry about return value here; if we errored out above then
|
|
* we want to communicate that value to the caller.
|
|
*/
|
|
(void) qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET);
|
|
QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER,
|
|
"%s: completed\n", __func__);
|
|
|
|
/*
|
|
* Blank the transfer state so we don't use an old transfer
|
|
* state in a subsequent interrupt.
|
|
*/
|
|
(void) qcom_spi_hw_complete_transfer(sc);
|
|
sc->transfer.active = false;
|
|
|
|
return (ret);
|
|
}
|
|
|
|
static int
|
|
qcom_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
|
|
{
|
|
struct qcom_spi_softc *sc = device_get_softc(dev);
|
|
uint32_t cs_val, mode_val, clock_val;
|
|
uint32_t ret = 0;
|
|
|
|
spibus_get_cs(child, &cs_val);
|
|
spibus_get_clock(child, &clock_val);
|
|
spibus_get_mode(child, &mode_val);
|
|
|
|
QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_TRANSFER,
|
|
"%s: called; child cs=0x%08x, clock=%u, mode=0x%08x, "
|
|
"cmd=%u/%u bytes; data=%u/%u bytes\n",
|
|
__func__,
|
|
cs_val,
|
|
clock_val,
|
|
mode_val,
|
|
cmd->tx_cmd_sz, cmd->rx_cmd_sz,
|
|
cmd->tx_data_sz, cmd->rx_data_sz);
|
|
|
|
QCOM_SPI_LOCK(sc);
|
|
|
|
/*
|
|
* wait until the controller isn't busy
|
|
*/
|
|
while (sc->sc_busy == true)
|
|
mtx_sleep(sc, &sc->sc_mtx, 0, "qcom_spi_wait", 0);
|
|
|
|
/*
|
|
* it's ours now!
|
|
*/
|
|
sc->sc_busy = true;
|
|
|
|
sc->state.cs_high = !! (cs_val & SPIBUS_CS_HIGH);
|
|
sc->state.frequency = clock_val;
|
|
|
|
/*
|
|
* We can't set the clock frequency and enable it
|
|
* with the driver lock held, as the SPI lock is non-sleepable
|
|
* and the clock framework is sleepable.
|
|
*
|
|
* No other transaction is going on right now, so we can
|
|
* unlock here and do the clock related work.
|
|
*/
|
|
QCOM_SPI_UNLOCK(sc);
|
|
|
|
/*
|
|
* Set the clock frequency
|
|
*/
|
|
ret = clk_set_freq(sc->clk_iface, sc->state.frequency, 0);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: failed to set frequency to %u\n",
|
|
sc->state.frequency);
|
|
goto done2;
|
|
}
|
|
clk_enable(sc->clk_iface);
|
|
|
|
QCOM_SPI_LOCK(sc);
|
|
|
|
/*
|
|
* Set state to RESET
|
|
*/
|
|
ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: can't transition to RESET (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
/* Assert hardware CS if set, else GPIO */
|
|
if (sc->cs_pins[cs_val & ~SPIBUS_CS_HIGH] == NULL)
|
|
qcom_spi_hw_spi_cs_force(sc, cs_val & SPIBUS_CS_HIGH, true);
|
|
else
|
|
qcom_spi_set_chipsel(sc, cs_val & ~SPIBUS_CS_HIGH, true);
|
|
|
|
/*
|
|
* cmd buffer transfer
|
|
*/
|
|
ret = qcom_spi_transfer_pio_block(sc, mode_val, cmd->tx_cmd,
|
|
cmd->tx_cmd_sz, cmd->rx_cmd, cmd->rx_cmd_sz);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: failed to transfer cmd payload (%u)\n", ret);
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* data buffer transfer
|
|
*/
|
|
if (cmd->tx_data_sz > 0) {
|
|
ret = qcom_spi_transfer_pio_block(sc, mode_val, cmd->tx_data,
|
|
cmd->tx_data_sz, cmd->rx_data, cmd->rx_data_sz);
|
|
if (ret != 0) {
|
|
device_printf(sc->sc_dev,
|
|
"ERROR: failed to transfer data payload (%u)\n",
|
|
ret);
|
|
goto done;
|
|
}
|
|
}
|
|
|
|
done:
|
|
/* De-assert GPIO/CS */
|
|
if (sc->cs_pins[cs_val & ~SPIBUS_CS_HIGH] == NULL)
|
|
qcom_spi_hw_spi_cs_force(sc, cs_val & ~SPIBUS_CS_HIGH, false);
|
|
else
|
|
qcom_spi_set_chipsel(sc, cs_val & ~SPIBUS_CS_HIGH, false);
|
|
|
|
/*
|
|
* Similarly to when we enabled the clock, we can't hold it here
|
|
* across a clk API as that's a sleep lock and we're non-sleepable.
|
|
* So instead we unlock/relock here, but we still hold the busy flag.
|
|
*/
|
|
|
|
QCOM_SPI_UNLOCK(sc);
|
|
clk_disable(sc->clk_iface);
|
|
QCOM_SPI_LOCK(sc);
|
|
done2:
|
|
/*
|
|
* We're done; so mark the bus as not busy and wakeup
|
|
* the next caller.
|
|
*/
|
|
sc->sc_busy = false;
|
|
wakeup_one(sc);
|
|
QCOM_SPI_UNLOCK(sc);
|
|
return (ret);
|
|
}
|
|
|
|
static int
|
|
qcom_spi_detach(device_t dev)
|
|
{
|
|
struct qcom_spi_softc *sc = device_get_softc(dev);
|
|
int i;
|
|
|
|
bus_generic_detach(sc->sc_dev);
|
|
if (sc->spibus != NULL)
|
|
device_delete_child(dev, sc->spibus);
|
|
|
|
if (sc->sc_irq_h)
|
|
bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
|
|
|
|
if (sc->clk_iface) {
|
|
clk_disable(sc->clk_iface);
|
|
clk_release(sc->clk_iface);
|
|
}
|
|
if (sc->clk_core) {
|
|
clk_disable(sc->clk_core);
|
|
clk_release(sc->clk_core);
|
|
}
|
|
|
|
for (i = 0; i < CS_MAX; i++) {
|
|
if (sc->cs_pins[i] != NULL)
|
|
gpio_pin_release(sc->cs_pins[i]);
|
|
}
|
|
|
|
if (sc->sc_mem_res)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
|
|
if (sc->sc_irq_res)
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
|
|
|
|
mtx_destroy(&sc->sc_mtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static phandle_t
|
|
qcom_spi_get_node(device_t bus, device_t dev)
|
|
{
|
|
|
|
return ofw_bus_get_node(bus);
|
|
}
|
|
|
|
|
|
static device_method_t qcom_spi_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, qcom_spi_probe),
|
|
DEVMETHOD(device_attach, qcom_spi_attach),
|
|
DEVMETHOD(device_detach, qcom_spi_detach),
|
|
/* TODO: suspend */
|
|
/* TODO: resume */
|
|
|
|
DEVMETHOD(spibus_transfer, qcom_spi_transfer),
|
|
|
|
/* ofw_bus_if */
|
|
DEVMETHOD(ofw_bus_get_node, qcom_spi_get_node),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t qcom_spi_driver = {
|
|
"qcom_spi",
|
|
qcom_spi_methods,
|
|
sizeof(struct qcom_spi_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(qcom_spi, simplebus, qcom_spi_driver, 0, 0);
|
|
DRIVER_MODULE(ofw_spibus, qcom_spi, ofw_spibus_driver, 0, 0);
|
|
MODULE_DEPEND(qcom_spi, ofw_spibus, 1, 1, 1);
|
|
SIMPLEBUS_PNP_INFO(compat_data);
|