401 lines
10 KiB
C
401 lines
10 KiB
C
/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright 2006 by Juniper Networks.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/serial.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <dev/ic/quicc.h>
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#include <dev/quicc/quicc_bfe.h>
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#include <dev/quicc/quicc_bus.h>
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#define quicc_read2(r, o) \
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bus_space_read_2((r)->r_bustag, (r)->r_bushandle, o)
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#define quicc_read4(r, o) \
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bus_space_read_4((r)->r_bustag, (r)->r_bushandle, o)
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#define quicc_write2(r, o, v) \
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bus_space_write_2((r)->r_bustag, (r)->r_bushandle, o, v)
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#define quicc_write4(r, o, v) \
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bus_space_write_4((r)->r_bustag, (r)->r_bushandle, o, v)
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char quicc_driver_name[] = "quicc";
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static MALLOC_DEFINE(M_QUICC, "QUICC", "QUICC driver");
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struct quicc_device {
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struct rman *qd_rman;
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struct resource_list qd_rlist;
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device_t qd_dev;
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int qd_devtype;
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driver_filter_t *qd_ih;
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void *qd_ih_arg;
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};
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static int
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quicc_bfe_intr(void *arg)
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{
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struct quicc_device *qd;
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struct quicc_softc *sc = arg;
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uint32_t sipnr;
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sipnr = quicc_read4(sc->sc_rres, QUICC_REG_SIPNR_L);
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if (sipnr & 0x00f00000)
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qd = sc->sc_device;
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else
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qd = NULL;
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if (qd == NULL || qd->qd_ih == NULL) {
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device_printf(sc->sc_dev, "Stray interrupt %08x\n", sipnr);
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return (FILTER_STRAY);
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}
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return ((*qd->qd_ih)(qd->qd_ih_arg));
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}
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int
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quicc_bfe_attach(device_t dev)
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{
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struct quicc_device *qd;
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struct quicc_softc *sc;
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struct resource_list_entry *rle;
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const char *sep;
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rman_res_t size, start;
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int error;
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sc = device_get_softc(dev);
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/*
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* Re-allocate. We expect that the softc contains the information
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* collected by quicc_bfe_probe() intact.
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*/
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sc->sc_rres = bus_alloc_resource_any(dev, sc->sc_rtype, &sc->sc_rrid,
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RF_ACTIVE);
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if (sc->sc_rres == NULL)
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return (ENXIO);
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start = rman_get_start(sc->sc_rres);
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size = rman_get_size(sc->sc_rres);
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sc->sc_rman.rm_start = start;
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sc->sc_rman.rm_end = start + size - 1;
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sc->sc_rman.rm_type = RMAN_ARRAY;
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sc->sc_rman.rm_descr = "QUICC resources";
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error = rman_init(&sc->sc_rman);
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if (!error)
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error = rman_manage_region(&sc->sc_rman, start,
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start + size - 1);
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if (error) {
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bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid,
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sc->sc_rres);
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return (error);
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}
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/*
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* Allocate interrupt resource.
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*/
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sc->sc_irid = 0;
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sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
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RF_ACTIVE | RF_SHAREABLE);
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if (sc->sc_ires != NULL) {
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error = bus_setup_intr(dev, sc->sc_ires,
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INTR_TYPE_TTY, quicc_bfe_intr, NULL, sc, &sc->sc_icookie);
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if (error) {
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error = bus_setup_intr(dev, sc->sc_ires,
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INTR_TYPE_TTY | INTR_MPSAFE, NULL,
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(driver_intr_t *)quicc_bfe_intr, sc,
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&sc->sc_icookie);
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} else
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sc->sc_fastintr = 1;
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if (error) {
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device_printf(dev, "could not activate interrupt\n");
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bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
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sc->sc_ires);
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sc->sc_ires = NULL;
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}
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}
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if (sc->sc_ires == NULL)
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sc->sc_polled = 1;
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if (bootverbose && (sc->sc_fastintr || sc->sc_polled)) {
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sep = "";
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device_print_prettyname(dev);
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if (sc->sc_fastintr) {
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printf("%sfast interrupt", sep);
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sep = ", ";
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}
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if (sc->sc_polled) {
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printf("%spolled mode", sep);
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sep = ", ";
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}
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printf("\n");
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}
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sc->sc_device = qd = malloc(sizeof(struct quicc_device), M_QUICC,
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M_WAITOK | M_ZERO);
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qd->qd_devtype = QUICC_DEVTYPE_SCC;
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qd->qd_rman = &sc->sc_rman;
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resource_list_init(&qd->qd_rlist);
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resource_list_add(&qd->qd_rlist, sc->sc_rtype, 0, start,
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start + size - 1, size);
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resource_list_add(&qd->qd_rlist, SYS_RES_IRQ, 0, 0xf00, 0xf00, 1);
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rle = resource_list_find(&qd->qd_rlist, SYS_RES_IRQ, 0);
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rle->res = sc->sc_ires;
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qd->qd_dev = device_add_child(dev, NULL, -1);
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device_set_ivars(qd->qd_dev, (void *)qd);
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error = device_probe_and_attach(qd->qd_dev);
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/* Enable all SCC interrupts. */
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quicc_write4(sc->sc_rres, QUICC_REG_SIMR_L, 0x00f00000);
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/* Clear all pending interrupts. */
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quicc_write4(sc->sc_rres, QUICC_REG_SIPNR_H, ~0);
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quicc_write4(sc->sc_rres, QUICC_REG_SIPNR_L, ~0);
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return (error);
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}
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int
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quicc_bfe_detach(device_t dev)
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{
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struct quicc_softc *sc;
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sc = device_get_softc(dev);
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bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie);
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bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid, sc->sc_ires);
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bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
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return (0);
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}
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int
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quicc_bfe_probe(device_t dev, u_int clock)
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{
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struct quicc_softc *sc;
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uint16_t rev;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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if (device_get_desc(dev) == NULL)
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device_set_desc(dev,
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"Quad integrated communications controller");
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sc->sc_rrid = 0;
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sc->sc_rtype = SYS_RES_MEMORY;
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sc->sc_rres = bus_alloc_resource_any(dev, sc->sc_rtype, &sc->sc_rrid,
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RF_ACTIVE);
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if (sc->sc_rres == NULL) {
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sc->sc_rrid = 0;
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sc->sc_rtype = SYS_RES_IOPORT;
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sc->sc_rres = bus_alloc_resource_any(dev, sc->sc_rtype,
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&sc->sc_rrid, RF_ACTIVE);
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if (sc->sc_rres == NULL)
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return (ENXIO);
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}
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sc->sc_clock = clock;
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/*
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* Check that the microcode revision is 0x00e8, as documented
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* in the MPC8555E PowerQUICC III Integrated Processor Family
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* Reference Manual.
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*/
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rev = quicc_read2(sc->sc_rres, QUICC_PRAM_REV_NUM);
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bus_release_resource(dev, sc->sc_rtype, sc->sc_rrid, sc->sc_rres);
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return ((rev == 0x00e8) ? BUS_PROBE_DEFAULT : ENXIO);
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}
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struct resource *
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quicc_bus_alloc_resource(device_t dev, device_t child, int type, int *rid,
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rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
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{
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struct quicc_device *qd;
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struct resource_list_entry *rle;
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if (device_get_parent(child) != dev)
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return (NULL);
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/* We only support default allocations. */
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if (!RMAN_IS_DEFAULT_RANGE(start, end))
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return (NULL);
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qd = device_get_ivars(child);
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rle = resource_list_find(&qd->qd_rlist, type, *rid);
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if (rle == NULL)
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return (NULL);
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if (rle->res == NULL) {
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rle->res = rman_reserve_resource(qd->qd_rman, rle->start,
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rle->start + rle->count - 1, rle->count, flags, child);
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if (rle->res != NULL) {
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rman_set_bustag(rle->res, &bs_be_tag);
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rman_set_bushandle(rle->res, rle->start);
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}
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}
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return (rle->res);
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}
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int
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quicc_bus_get_resource(device_t dev, device_t child, int type, int rid,
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rman_res_t *startp, rman_res_t *countp)
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{
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struct quicc_device *qd;
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struct resource_list_entry *rle;
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if (device_get_parent(child) != dev)
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return (EINVAL);
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qd = device_get_ivars(child);
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rle = resource_list_find(&qd->qd_rlist, type, rid);
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if (rle == NULL)
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return (EINVAL);
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if (startp != NULL)
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*startp = rle->start;
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if (countp != NULL)
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*countp = rle->count;
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return (0);
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}
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int
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quicc_bus_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
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{
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struct quicc_device *qd;
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struct quicc_softc *sc;
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uint32_t sccr;
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if (device_get_parent(child) != dev)
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return (EINVAL);
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sc = device_get_softc(dev);
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qd = device_get_ivars(child);
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switch (index) {
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case QUICC_IVAR_CLOCK:
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*result = sc->sc_clock;
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break;
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case QUICC_IVAR_BRGCLK:
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sccr = quicc_read4(sc->sc_rres, QUICC_REG_SCCR) & 3;
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*result = sc->sc_clock / ((1 << (sccr + 1)) << sccr);
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break;
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case QUICC_IVAR_DEVTYPE:
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*result = qd->qd_devtype;
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break;
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default:
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return (EINVAL);
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}
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return (0);
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}
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int
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quicc_bus_release_resource(device_t dev, device_t child, int type, int rid,
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struct resource *res)
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{
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struct quicc_device *qd;
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struct resource_list_entry *rle;
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if (device_get_parent(child) != dev)
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return (EINVAL);
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qd = device_get_ivars(child);
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rle = resource_list_find(&qd->qd_rlist, type, rid);
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return ((rle == NULL) ? EINVAL : 0);
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}
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int
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quicc_bus_setup_intr(device_t dev, device_t child, struct resource *r,
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int flags, driver_filter_t *filt, void (*ihand)(void *), void *arg,
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void **cookiep)
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{
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struct quicc_device *qd;
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struct quicc_softc *sc;
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if (device_get_parent(child) != dev)
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return (EINVAL);
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/* Interrupt handlers must be FAST or MPSAFE. */
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if (filt == NULL && !(flags & INTR_MPSAFE))
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return (EINVAL);
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sc = device_get_softc(dev);
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if (sc->sc_polled)
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return (ENXIO);
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if (sc->sc_fastintr && filt == NULL) {
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sc->sc_fastintr = 0;
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bus_teardown_intr(dev, sc->sc_ires, sc->sc_icookie);
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bus_setup_intr(dev, sc->sc_ires, INTR_TYPE_TTY | INTR_MPSAFE,
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NULL, (driver_intr_t *)quicc_bfe_intr, sc, &sc->sc_icookie);
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}
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qd = device_get_ivars(child);
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qd->qd_ih = (filt != NULL) ? filt : (driver_filter_t *)ihand;
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qd->qd_ih_arg = arg;
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*cookiep = ihand;
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return (0);
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}
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int
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quicc_bus_teardown_intr(device_t dev, device_t child, struct resource *r,
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void *cookie)
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{
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struct quicc_device *qd;
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if (device_get_parent(child) != dev)
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return (EINVAL);
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qd = device_get_ivars(child);
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if (qd->qd_ih != cookie)
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return (EINVAL);
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qd->qd_ih = NULL;
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qd->qd_ih_arg = NULL;
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return (0);
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}
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