518 lines
14 KiB
C
518 lines
14 KiB
C
/*
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* Copyright (C) 2015 Cavium Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef NIC_H
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#define NIC_H
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/* PCI vendor ID */
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#define PCI_VENDOR_ID_CAVIUM 0x177D
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/* PCI device IDs */
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#define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E
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#define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011
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#define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034
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#define PCI_DEVICE_ID_THUNDER_BGX 0xA026
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/* PCI BAR nos */
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#define PCI_CFG_REG_BAR_NUM 0
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#define PCI_MSIX_REG_BAR_NUM 4
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/* PCI revision IDs */
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#define PCI_REVID_PASS2 8
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/* NIC SRIOV VF count */
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#define MAX_NUM_VFS_SUPPORTED 128
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#define DEFAULT_NUM_VF_ENABLED 8
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#define NIC_TNS_BYPASS_MODE 0
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#define NIC_TNS_MODE 1
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/* NIC priv flags */
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#define NIC_SRIOV_ENABLED (1 << 0)
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#define NIC_TNS_ENABLED (1 << 1)
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/* ARM64TODO */
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#if 0
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/* VNIC HW optimiation features */
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#define VNIC_RSS_SUPPORT
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#define VNIC_MULTI_QSET_SUPPORT
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#endif
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/* Min/Max packet size */
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#define NIC_HW_MIN_FRS 64
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#define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */
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/* Max pkinds */
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#define NIC_MAX_PKIND 16
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/*
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* Rx Channels */
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/* Receive channel configuration in TNS bypass mode
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* Below is configuration in TNS bypass mode
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* BGX0-LMAC0-CHAN0 - VNIC CHAN0
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* BGX0-LMAC1-CHAN0 - VNIC CHAN16
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* ...
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* BGX1-LMAC0-CHAN0 - VNIC CHAN128
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* ...
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* BGX1-LMAC3-CHAN0 - VNIC CHAN174
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*/
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#define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */
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#define NIC_CHANS_PER_INF 128
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#define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF)
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#define NIC_CPI_COUNT 2048 /* No of channel parse indices */
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/* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */
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#define NIC_MAX_BGX MAX_BGX_PER_CN88XX
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#define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX)
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#define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */
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#define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX)
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/* Tx scheduling */
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#define NIC_MAX_TL4 1024
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#define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */
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#define NIC_MAX_TL3 256
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#define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */
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#define NIC_MAX_TL2 64
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#define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */
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#define NIC_MAX_TL1 2
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/* TNS bypass mode */
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#define NIC_TL2_PER_BGX 32
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#define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX)
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#define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF)
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/* NIC VF Interrupts */
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#define NICVF_INTR_CQ 0
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#define NICVF_INTR_SQ 1
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#define NICVF_INTR_RBDR 2
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#define NICVF_INTR_PKT_DROP 3
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#define NICVF_INTR_TCP_TIMER 4
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#define NICVF_INTR_MBOX 5
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#define NICVF_INTR_QS_ERR 6
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#define NICVF_INTR_CQ_SHIFT 0
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#define NICVF_INTR_SQ_SHIFT 8
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#define NICVF_INTR_RBDR_SHIFT 16
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#define NICVF_INTR_PKT_DROP_SHIFT 20
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#define NICVF_INTR_TCP_TIMER_SHIFT 21
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#define NICVF_INTR_MBOX_SHIFT 22
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#define NICVF_INTR_QS_ERR_SHIFT 23
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#define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
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#define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
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#define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
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#define NICVF_INTR_PKT_DROP_MASK (1 << NICVF_INTR_PKT_DROP_SHIFT)
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#define NICVF_INTR_TCP_TIMER_MASK (1 << NICVF_INTR_TCP_TIMER_SHIFT)
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#define NICVF_INTR_MBOX_MASK (1 << NICVF_INTR_MBOX_SHIFT)
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#define NICVF_INTR_QS_ERR_MASK (1 << NICVF_INTR_QS_ERR_SHIFT)
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/* MSI-X interrupts */
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#define NIC_PF_MSIX_VECTORS 10
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#define NIC_VF_MSIX_VECTORS 20
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#define NIC_PF_INTR_ID_ECC0_SBE 0
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#define NIC_PF_INTR_ID_ECC0_DBE 1
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#define NIC_PF_INTR_ID_ECC1_SBE 2
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#define NIC_PF_INTR_ID_ECC1_DBE 3
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#define NIC_PF_INTR_ID_ECC2_SBE 4
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#define NIC_PF_INTR_ID_ECC2_DBE 5
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#define NIC_PF_INTR_ID_ECC3_SBE 6
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#define NIC_PF_INTR_ID_ECC3_DBE 7
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#define NIC_PF_INTR_ID_MBOX0 8
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#define NIC_PF_INTR_ID_MBOX1 9
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struct msix_entry {
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struct resource * irq_res;
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void * handle;
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};
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/*
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* Global timer for CQ timer thresh interrupts
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* Calculated for SCLK of 700Mhz
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* value written should be a 1/16th of what is expected
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*
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* 1 tick per 0.05usec = value of 2.2
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* This 10% would be covered in CQ timer thresh value
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*/
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#define NICPF_CLK_PER_INT_TICK 2
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/*
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* Time to wait before we decide that a SQ is stuck.
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*
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* Since both pkt rx and tx notifications are done with same CQ,
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* when packets are being received at very high rate (eg: L2 forwarding)
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* then freeing transmitted skbs will be delayed and watchdog
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* will kick in, resetting interface. Hence keeping this value high.
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*/
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#define NICVF_TX_TIMEOUT (50 * HZ)
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#define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */
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#define NIC_MAX_RSS_HASH_BITS 8
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#define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS)
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#define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
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struct nicvf_rss_info {
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boolean_t enable;
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#define RSS_L2_EXTENDED_HASH_ENA (1UL << 0)
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#define RSS_IP_HASH_ENA (1UL << 1)
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#define RSS_TCP_HASH_ENA (1UL << 2)
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#define RSS_TCP_SYN_DIS (1UL << 3)
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#define RSS_UDP_HASH_ENA (1UL << 4)
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#define RSS_L4_EXTENDED_HASH_ENA (1UL << 5)
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#define RSS_ROCE_ENA (1UL << 6)
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#define RSS_L3_BI_DIRECTION_ENA (1UL << 7)
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#define RSS_L4_BI_DIRECTION_ENA (1UL << 8)
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uint64_t cfg;
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uint8_t hash_bits;
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uint16_t rss_size;
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uint8_t ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
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uint64_t key[RSS_HASH_KEY_SIZE];
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};
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enum rx_stats_reg_offset {
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RX_OCTS = 0x0,
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RX_UCAST = 0x1,
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RX_BCAST = 0x2,
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RX_MCAST = 0x3,
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RX_RED = 0x4,
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RX_RED_OCTS = 0x5,
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RX_ORUN = 0x6,
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RX_ORUN_OCTS = 0x7,
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RX_FCS = 0x8,
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RX_L2ERR = 0x9,
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RX_DRP_BCAST = 0xa,
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RX_DRP_MCAST = 0xb,
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RX_DRP_L3BCAST = 0xc,
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RX_DRP_L3MCAST = 0xd,
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RX_STATS_ENUM_LAST,
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};
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enum tx_stats_reg_offset {
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TX_OCTS = 0x0,
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TX_UCAST = 0x1,
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TX_BCAST = 0x2,
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TX_MCAST = 0x3,
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TX_DROP = 0x4,
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TX_STATS_ENUM_LAST,
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};
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struct nicvf_hw_stats {
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uint64_t rx_bytes;
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uint64_t rx_ucast_frames;
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uint64_t rx_bcast_frames;
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uint64_t rx_mcast_frames;
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uint64_t rx_fcs_errors;
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uint64_t rx_l2_errors;
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uint64_t rx_drop_red;
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uint64_t rx_drop_red_bytes;
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uint64_t rx_drop_overrun;
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uint64_t rx_drop_overrun_bytes;
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uint64_t rx_drop_bcast;
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uint64_t rx_drop_mcast;
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uint64_t rx_drop_l3_bcast;
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uint64_t rx_drop_l3_mcast;
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uint64_t rx_bgx_truncated_pkts;
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uint64_t rx_jabber_errs;
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uint64_t rx_fcs_errs;
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uint64_t rx_bgx_errs;
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uint64_t rx_prel2_errs;
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uint64_t rx_l2_hdr_malformed;
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uint64_t rx_oversize;
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uint64_t rx_undersize;
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uint64_t rx_l2_len_mismatch;
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uint64_t rx_l2_pclp;
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uint64_t rx_ip_ver_errs;
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uint64_t rx_ip_csum_errs;
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uint64_t rx_ip_hdr_malformed;
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uint64_t rx_ip_payload_malformed;
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uint64_t rx_ip_ttl_errs;
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uint64_t rx_l3_pclp;
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uint64_t rx_l4_malformed;
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uint64_t rx_l4_csum_errs;
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uint64_t rx_udp_len_errs;
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uint64_t rx_l4_port_errs;
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uint64_t rx_tcp_flag_errs;
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uint64_t rx_tcp_offset_errs;
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uint64_t rx_l4_pclp;
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uint64_t rx_truncated_pkts;
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uint64_t tx_bytes_ok;
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uint64_t tx_ucast_frames_ok;
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uint64_t tx_bcast_frames_ok;
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uint64_t tx_mcast_frames_ok;
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uint64_t tx_drops;
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};
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struct nicvf_drv_stats {
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/* Rx */
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uint64_t rx_frames_ok;
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uint64_t rx_frames_64;
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uint64_t rx_frames_127;
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uint64_t rx_frames_255;
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uint64_t rx_frames_511;
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uint64_t rx_frames_1023;
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uint64_t rx_frames_1518;
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uint64_t rx_frames_jumbo;
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uint64_t rx_drops;
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/* Tx */
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uint64_t tx_frames_ok;
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uint64_t tx_drops;
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uint64_t tx_tso;
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uint64_t txq_stop;
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uint64_t txq_wake;
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};
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struct nicvf {
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struct nicvf *pnicvf;
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device_t dev;
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if_t ifp;
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struct sx core_sx;
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struct ifmedia if_media;
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uint32_t if_flags;
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uint8_t hwaddr[ETHER_ADDR_LEN];
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uint8_t vf_id;
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uint8_t node;
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boolean_t tns_mode:1;
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boolean_t sqs_mode:1;
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bool loopback_supported:1;
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struct nicvf_rss_info rss_info;
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uint16_t mtu;
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struct queue_set *qs;
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uint8_t rx_queues;
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uint8_t tx_queues;
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uint8_t max_queues;
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struct resource *reg_base;
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boolean_t link_up;
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boolean_t hw_tso;
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uint8_t duplex;
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uint32_t speed;
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uint8_t cpi_alg;
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/* Interrupt coalescing settings */
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uint32_t cq_coalesce_usecs;
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uint32_t msg_enable;
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struct nicvf_hw_stats hw_stats;
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struct nicvf_drv_stats drv_stats;
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struct bgx_stats bgx_stats;
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/* Interface statistics */
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struct callout stats_callout;
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struct mtx stats_mtx;
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/* MSI-X */
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boolean_t msix_enabled;
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uint8_t num_vec;
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struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS];
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struct resource * msix_table_res;
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char irq_name[NIC_VF_MSIX_VECTORS][20];
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boolean_t irq_allocated[NIC_VF_MSIX_VECTORS];
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/* VF <-> PF mailbox communication */
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boolean_t pf_acked;
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boolean_t pf_nacked;
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} __aligned(CACHE_LINE_SIZE);
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/*
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* PF <--> VF Mailbox communication
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* Eight 64bit registers are shared between PF and VF.
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* Separate set for each VF.
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* Writing '1' into last register mbx7 means end of message.
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*/
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/* PF <--> VF mailbox communication */
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#define NIC_PF_VF_MAILBOX_SIZE 2
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#define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */
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/* Mailbox message types */
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#define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */
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#define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */
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#define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */
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#define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */
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#define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */
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#define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */
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#define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */
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#define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */
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#define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */
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#define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */
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#define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */
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#define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */
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#define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */
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#define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */
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#define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */
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#define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */
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#define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */
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#define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */
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#define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */
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#define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */
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#define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */
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#define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */
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#define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */
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#define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */
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struct nic_cfg_msg {
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uint8_t msg;
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uint8_t vf_id;
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uint8_t node_id;
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boolean_t tns_mode:1;
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boolean_t sqs_mode:1;
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boolean_t loopback_supported:1;
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uint8_t mac_addr[ETHER_ADDR_LEN];
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};
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/* Qset configuration */
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struct qs_cfg_msg {
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uint8_t msg;
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uint8_t num;
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uint8_t sqs_count;
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uint64_t cfg;
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};
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/* Receive queue configuration */
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struct rq_cfg_msg {
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uint8_t msg;
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uint8_t qs_num;
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uint8_t rq_num;
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uint64_t cfg;
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};
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/* Send queue configuration */
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struct sq_cfg_msg {
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uint8_t msg;
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uint8_t qs_num;
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uint8_t sq_num;
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boolean_t sqs_mode;
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uint64_t cfg;
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};
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/* Set VF's MAC address */
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struct set_mac_msg {
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uint8_t msg;
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uint8_t vf_id;
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uint8_t mac_addr[ETHER_ADDR_LEN];
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};
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/* Set Maximum frame size */
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struct set_frs_msg {
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uint8_t msg;
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uint8_t vf_id;
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uint16_t max_frs;
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};
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/* Set CPI algorithm type */
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struct cpi_cfg_msg {
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uint8_t msg;
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uint8_t vf_id;
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uint8_t rq_cnt;
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uint8_t cpi_alg;
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};
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/* Get RSS table size */
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struct rss_sz_msg {
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uint8_t msg;
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uint8_t vf_id;
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uint16_t ind_tbl_size;
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};
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/* Set RSS configuration */
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struct rss_cfg_msg {
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uint8_t msg;
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uint8_t vf_id;
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uint8_t hash_bits;
|
|
uint8_t tbl_len;
|
|
uint8_t tbl_offset;
|
|
#define RSS_IND_TBL_LEN_PER_MBX_MSG 8
|
|
uint8_t ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG];
|
|
};
|
|
|
|
struct bgx_stats_msg {
|
|
uint8_t msg;
|
|
uint8_t vf_id;
|
|
uint8_t rx;
|
|
uint8_t idx;
|
|
uint64_t stats;
|
|
};
|
|
|
|
/* Physical interface link status */
|
|
struct bgx_link_status {
|
|
uint8_t msg;
|
|
uint8_t link_up;
|
|
uint8_t duplex;
|
|
uint32_t speed;
|
|
};
|
|
|
|
/* Set interface in loopback mode */
|
|
struct set_loopback {
|
|
uint8_t msg;
|
|
uint8_t vf_id;
|
|
boolean_t enable;
|
|
};
|
|
|
|
/* 128 bit shared memory between PF and each VF */
|
|
union nic_mbx {
|
|
struct {
|
|
uint8_t msg;
|
|
} msg;
|
|
struct nic_cfg_msg nic_cfg;
|
|
struct qs_cfg_msg qs;
|
|
struct rq_cfg_msg rq;
|
|
struct sq_cfg_msg sq;
|
|
struct set_mac_msg mac;
|
|
struct set_frs_msg frs;
|
|
struct cpi_cfg_msg cpi_cfg;
|
|
struct rss_sz_msg rss_size;
|
|
struct rss_cfg_msg rss_cfg;
|
|
struct bgx_stats_msg bgx_stats;
|
|
struct bgx_link_status link_status;
|
|
struct set_loopback lbk;
|
|
};
|
|
|
|
#define NIC_NODE_ID_MASK 0x03
|
|
#define NIC_NODE_ID_SHIFT 44
|
|
|
|
static __inline int
|
|
nic_get_node_id(struct resource *res)
|
|
{
|
|
pci_addr_t addr;
|
|
|
|
addr = rman_get_start(res);
|
|
return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK);
|
|
}
|
|
|
|
static __inline boolean_t
|
|
pass1_silicon(device_t dev)
|
|
{
|
|
|
|
/* Check if the chip revision is < Pass2 */
|
|
return (pci_get_revid(dev) < PCI_REVID_PASS2);
|
|
}
|
|
|
|
int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx);
|
|
|
|
#endif /* NIC_H */
|