1140 lines
29 KiB
C
1140 lines
29 KiB
C
/*
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* Copyright (C) 2015 Cavium Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bitset.h>
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#include <sys/bitstring.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/pciio.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/cpuset.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include "thunder_bgx.h"
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#include "thunder_bgx_var.h"
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#include "nic_reg.h"
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#include "nic.h"
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#include "lmac_if.h"
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#define THUNDER_BGX_DEVSTR "ThunderX BGX Ethernet I/O Interface"
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MALLOC_DEFINE(M_BGX, "thunder_bgx", "ThunderX BGX dynamic memory");
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#define BGX_NODE_ID_MASK 0x1
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#define BGX_NODE_ID_SHIFT 24
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#define DRV_NAME "thunder-BGX"
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#define DRV_VERSION "1.0"
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static int bgx_init_phy(struct bgx *);
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static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
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static int lmac_count __unused; /* Total no of LMACs in system */
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static int bgx_xaui_check_link(struct lmac *lmac);
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static void bgx_get_qlm_mode(struct bgx *);
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static void bgx_init_hw(struct bgx *);
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static int bgx_lmac_enable(struct bgx *, uint8_t);
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static void bgx_lmac_disable(struct bgx *, uint8_t);
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static int thunder_bgx_probe(device_t);
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static int thunder_bgx_attach(device_t);
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static int thunder_bgx_detach(device_t);
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static device_method_t thunder_bgx_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, thunder_bgx_probe),
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DEVMETHOD(device_attach, thunder_bgx_attach),
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DEVMETHOD(device_detach, thunder_bgx_detach),
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DEVMETHOD_END,
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};
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static driver_t thunder_bgx_driver = {
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"bgx",
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thunder_bgx_methods,
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sizeof(struct lmac),
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};
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DRIVER_MODULE(thunder_bgx, pci, thunder_bgx_driver, 0, 0);
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MODULE_VERSION(thunder_bgx, 1);
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MODULE_DEPEND(thunder_bgx, pci, 1, 1, 1);
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MODULE_DEPEND(thunder_bgx, ether, 1, 1, 1);
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MODULE_DEPEND(thunder_bgx, thunder_mdio, 1, 1, 1);
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static int
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thunder_bgx_probe(device_t dev)
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{
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uint16_t vendor_id;
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uint16_t device_id;
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vendor_id = pci_get_vendor(dev);
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device_id = pci_get_device(dev);
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if (vendor_id == PCI_VENDOR_ID_CAVIUM &&
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device_id == PCI_DEVICE_ID_THUNDER_BGX) {
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device_set_desc(dev, THUNDER_BGX_DEVSTR);
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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thunder_bgx_attach(device_t dev)
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{
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struct bgx *bgx;
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uint8_t lmacid;
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int err;
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int rid;
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struct lmac *lmac;
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bgx = malloc(sizeof(*bgx), M_BGX, (M_WAITOK | M_ZERO));
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bgx->dev = dev;
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lmac = device_get_softc(dev);
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lmac->bgx = bgx;
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/* Enable bus mastering */
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pci_enable_busmaster(dev);
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/* Allocate resources - configuration registers */
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rid = PCIR_BAR(PCI_CFG_REG_BAR_NUM);
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bgx->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (bgx->reg_base == NULL) {
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device_printf(dev, "Could not allocate CSR memory space\n");
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err = ENXIO;
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goto err_disable_device;
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}
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bgx->bgx_id = (rman_get_start(bgx->reg_base) >> BGX_NODE_ID_SHIFT) &
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BGX_NODE_ID_MASK;
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bgx->bgx_id += nic_get_node_id(bgx->reg_base) * MAX_BGX_PER_CN88XX;
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bgx_vnic[bgx->bgx_id] = bgx;
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bgx_get_qlm_mode(bgx);
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err = bgx_init_phy(bgx);
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if (err != 0)
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goto err_free_res;
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bgx_init_hw(bgx);
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/* Enable all LMACs */
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for (lmacid = 0; lmacid < bgx->lmac_count; lmacid++) {
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err = bgx_lmac_enable(bgx, lmacid);
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if (err) {
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device_printf(dev, "BGX%d failed to enable lmac%d\n",
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bgx->bgx_id, lmacid);
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goto err_free_res;
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}
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}
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return (0);
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err_free_res:
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bgx_vnic[bgx->bgx_id] = NULL;
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(bgx->reg_base), bgx->reg_base);
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err_disable_device:
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free(bgx, M_BGX);
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pci_disable_busmaster(dev);
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return (err);
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}
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static int
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thunder_bgx_detach(device_t dev)
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{
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struct lmac *lmac;
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struct bgx *bgx;
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uint8_t lmacid;
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lmac = device_get_softc(dev);
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bgx = lmac->bgx;
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/* Disable all LMACs */
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for (lmacid = 0; lmacid < bgx->lmac_count; lmacid++)
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bgx_lmac_disable(bgx, lmacid);
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bgx_vnic[bgx->bgx_id] = NULL;
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(bgx->reg_base), bgx->reg_base);
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free(bgx, M_BGX);
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pci_disable_busmaster(dev);
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return (0);
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}
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/* Register read/write APIs */
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static uint64_t
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bgx_reg_read(struct bgx *bgx, uint8_t lmac, uint64_t offset)
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{
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bus_space_handle_t addr;
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addr = ((uint32_t)lmac << 20) + offset;
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return (bus_read_8(bgx->reg_base, addr));
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}
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static void
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bgx_reg_write(struct bgx *bgx, uint8_t lmac, uint64_t offset, uint64_t val)
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{
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bus_space_handle_t addr;
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addr = ((uint32_t)lmac << 20) + offset;
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bus_write_8(bgx->reg_base, addr, val);
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}
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static void
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bgx_reg_modify(struct bgx *bgx, uint8_t lmac, uint64_t offset, uint64_t val)
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{
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bus_space_handle_t addr;
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addr = ((uint32_t)lmac << 20) + offset;
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bus_write_8(bgx->reg_base, addr, val | bus_read_8(bgx->reg_base, addr));
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}
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static int
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bgx_poll_reg(struct bgx *bgx, uint8_t lmac, uint64_t reg, uint64_t mask,
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boolean_t zero)
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{
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int timeout = 10;
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uint64_t reg_val;
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while (timeout) {
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reg_val = bgx_reg_read(bgx, lmac, reg);
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if (zero && !(reg_val & mask))
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return (0);
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if (!zero && (reg_val & mask))
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return (0);
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DELAY(100);
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timeout--;
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}
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return (ETIMEDOUT);
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}
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/* Return number of BGX present in HW */
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u_int
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bgx_get_map(int node)
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{
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int i;
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u_int map = 0;
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for (i = 0; i < MAX_BGX_PER_CN88XX; i++) {
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if (bgx_vnic[(node * MAX_BGX_PER_CN88XX) + i])
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map |= (1 << i);
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}
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return (map);
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}
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/* Return number of LMAC configured for this BGX */
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int
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bgx_get_lmac_count(int node, int bgx_idx)
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{
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struct bgx *bgx;
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bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
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if (bgx != NULL)
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return (bgx->lmac_count);
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return (0);
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}
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/* Returns the current link status of LMAC */
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void
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bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
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{
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struct bgx_link_status *link = (struct bgx_link_status *)status;
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struct bgx *bgx;
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struct lmac *lmac;
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bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
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if (bgx == NULL)
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return;
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lmac = &bgx->lmac[lmacid];
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link->link_up = lmac->link_up;
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link->duplex = lmac->last_duplex;
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link->speed = lmac->last_speed;
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}
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const uint8_t
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*bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
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{
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struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
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if (bgx != NULL)
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return (bgx->lmac[lmacid].mac);
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return (NULL);
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}
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void
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bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const uint8_t *mac)
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{
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struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
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if (bgx == NULL)
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return;
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memcpy(bgx->lmac[lmacid].mac, mac, ETHER_ADDR_LEN);
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}
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static void
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bgx_sgmii_change_link_state(struct lmac *lmac)
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{
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struct bgx *bgx = lmac->bgx;
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uint64_t cmr_cfg;
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uint64_t port_cfg = 0;
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uint64_t misc_ctl = 0;
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cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
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cmr_cfg &= ~CMR_EN;
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bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
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port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
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misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
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if (lmac->link_up) {
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misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
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port_cfg &= ~GMI_PORT_CFG_DUPLEX;
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port_cfg |= (lmac->last_duplex << 2);
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} else {
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misc_ctl |= PCS_MISC_CTL_GMX_ENO;
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}
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switch (lmac->last_speed) {
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case 10:
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port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
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port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
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port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
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misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
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misc_ctl |= 50; /* samp_pt */
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bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
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bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
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break;
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case 100:
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port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
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port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
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port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
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misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
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misc_ctl |= 5; /* samp_pt */
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bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
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bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
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break;
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case 1000:
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port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
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port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
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port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
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misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
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misc_ctl |= 1; /* samp_pt */
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bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
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if (lmac->last_duplex)
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bgx_reg_write(bgx, lmac->lmacid,
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BGX_GMP_GMI_TXX_BURST, 0);
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else
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bgx_reg_write(bgx, lmac->lmacid,
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BGX_GMP_GMI_TXX_BURST, 8192);
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break;
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default:
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break;
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}
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bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
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bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
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port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
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/* renable lmac */
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cmr_cfg |= CMR_EN;
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bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
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}
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static void
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bgx_lmac_handler(void *arg)
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{
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struct lmac *lmac;
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int link, duplex, speed;
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int link_changed = 0;
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int err;
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lmac = (struct lmac *)arg;
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err = LMAC_MEDIA_STATUS(lmac->phy_if_dev, lmac->lmacid,
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&link, &duplex, &speed);
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if (err != 0)
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goto out;
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if (!link && lmac->last_link)
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link_changed = -1;
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if (link &&
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(lmac->last_duplex != duplex ||
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lmac->last_link != link ||
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lmac->last_speed != speed)) {
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link_changed = 1;
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}
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lmac->last_link = link;
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lmac->last_speed = speed;
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lmac->last_duplex = duplex;
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if (!link_changed)
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goto out;
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if (link_changed > 0)
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lmac->link_up = true;
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else
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lmac->link_up = false;
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if (lmac->is_sgmii)
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bgx_sgmii_change_link_state(lmac);
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else
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bgx_xaui_check_link(lmac);
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out:
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callout_reset(&lmac->check_link, hz * 2, bgx_lmac_handler, lmac);
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}
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uint64_t
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bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
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{
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struct bgx *bgx;
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bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
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if (bgx == NULL)
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return (0);
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if (idx > 8)
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lmac = (0);
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return (bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8)));
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}
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uint64_t
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bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
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{
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struct bgx *bgx;
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bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
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if (bgx == NULL)
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return (0);
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return (bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8)));
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}
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static void
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bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
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{
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uint64_t offset;
|
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while (bgx->lmac[lmac].dmac > 0) {
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offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(uint64_t)) +
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(lmac * MAX_DMAC_PER_LMAC * sizeof(uint64_t));
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bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
|
|
bgx->lmac[lmac].dmac--;
|
|
}
|
|
}
|
|
|
|
void
|
|
bgx_add_dmac_addr(uint64_t dmac, int node, int bgx_idx, int lmac)
|
|
{
|
|
uint64_t offset;
|
|
struct bgx *bgx;
|
|
|
|
#ifdef BGX_IN_PROMISCUOUS_MODE
|
|
return;
|
|
#endif
|
|
|
|
bgx_idx += node * MAX_BGX_PER_CN88XX;
|
|
bgx = bgx_vnic[bgx_idx];
|
|
|
|
if (bgx == NULL) {
|
|
printf("BGX%d not yet initialized, ignoring DMAC addition\n",
|
|
bgx_idx);
|
|
return;
|
|
}
|
|
|
|
dmac = dmac | (1UL << 48) | ((uint64_t)lmac << 49); /* Enable DMAC */
|
|
if (bgx->lmac[lmac].dmac == MAX_DMAC_PER_LMAC) {
|
|
device_printf(bgx->dev,
|
|
"Max DMAC filters for LMAC%d reached, ignoring\n",
|
|
lmac);
|
|
return;
|
|
}
|
|
|
|
if (bgx->lmac[lmac].dmac == MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE)
|
|
bgx->lmac[lmac].dmac = 1;
|
|
|
|
offset = (bgx->lmac[lmac].dmac * sizeof(uint64_t)) +
|
|
(lmac * MAX_DMAC_PER_LMAC * sizeof(uint64_t));
|
|
bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, dmac);
|
|
bgx->lmac[lmac].dmac++;
|
|
|
|
bgx_reg_write(bgx, lmac, BGX_CMRX_RX_DMAC_CTL,
|
|
(CAM_ACCEPT << 3) | (MCAST_MODE_CAM_FILTER << 1) |
|
|
(BCAST_ACCEPT << 0));
|
|
}
|
|
|
|
/* Configure BGX LMAC in internal loopback mode */
|
|
void
|
|
bgx_lmac_internal_loopback(int node, int bgx_idx,
|
|
int lmac_idx, boolean_t enable)
|
|
{
|
|
struct bgx *bgx;
|
|
struct lmac *lmac;
|
|
uint64_t cfg;
|
|
|
|
bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
|
|
if (bgx == NULL)
|
|
return;
|
|
|
|
lmac = &bgx->lmac[lmac_idx];
|
|
if (lmac->is_sgmii) {
|
|
cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
|
|
if (enable)
|
|
cfg |= PCS_MRX_CTL_LOOPBACK1;
|
|
else
|
|
cfg &= ~PCS_MRX_CTL_LOOPBACK1;
|
|
bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
|
|
} else {
|
|
cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
|
|
if (enable)
|
|
cfg |= SPU_CTL_LOOPBACK;
|
|
else
|
|
cfg &= ~SPU_CTL_LOOPBACK;
|
|
bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
|
|
}
|
|
}
|
|
|
|
static int
|
|
bgx_lmac_sgmii_init(struct bgx *bgx, int lmacid)
|
|
{
|
|
uint64_t cfg;
|
|
|
|
bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
|
|
/* max packet size */
|
|
bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
|
|
|
|
/* Disable frame alignment if using preamble */
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
|
|
if (cfg & 1)
|
|
bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
|
|
|
|
/* Enable lmac */
|
|
bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
|
|
|
|
/* PCS reset */
|
|
bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
|
|
if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
|
|
PCS_MRX_CTL_RESET, TRUE) != 0) {
|
|
device_printf(bgx->dev, "BGX PCS reset not completed\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* power down, reset autoneg, autoneg enable */
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
|
|
cfg &= ~PCS_MRX_CTL_PWR_DN;
|
|
cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN);
|
|
bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
|
|
|
|
if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
|
|
PCS_MRX_STATUS_AN_CPT, FALSE) != 0) {
|
|
device_printf(bgx->dev, "BGX AN_CPT not completed\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
bgx_lmac_xaui_init(struct bgx *bgx, int lmacid, int lmac_type)
|
|
{
|
|
uint64_t cfg;
|
|
|
|
/* Reset SPU */
|
|
bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
|
|
if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1,
|
|
SPU_CTL_RESET, TRUE) != 0) {
|
|
device_printf(bgx->dev, "BGX SPU reset not completed\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Disable LMAC */
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
|
|
cfg &= ~CMR_EN;
|
|
bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
|
|
|
|
bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
|
|
/* Set interleaved running disparity for RXAUI */
|
|
if (bgx->lmac_type != BGX_MODE_RXAUI) {
|
|
bgx_reg_modify(bgx, lmacid,
|
|
BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
|
|
} else {
|
|
bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
|
|
SPU_MISC_CTL_RX_DIS | SPU_MISC_CTL_INTLV_RDISP);
|
|
}
|
|
|
|
/* clear all interrupts */
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
|
|
bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
|
|
bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
|
|
|
|
if (bgx->use_training) {
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
|
|
/* training enable */
|
|
bgx_reg_modify(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL,
|
|
SPU_PMD_CRTL_TRAIN_EN);
|
|
}
|
|
|
|
/* Append FCS to each packet */
|
|
bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
|
|
|
|
/* Disable forward error correction */
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
|
|
cfg &= ~SPU_FEC_CTL_FEC_EN;
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
|
|
|
|
/* Disable autoneg */
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
|
|
cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
|
|
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
|
|
if (bgx->lmac_type == BGX_MODE_10G_KR)
|
|
cfg |= (1 << 23);
|
|
else if (bgx->lmac_type == BGX_MODE_40G_KR)
|
|
cfg |= (1 << 24);
|
|
else
|
|
cfg &= ~((1 << 23) | (1 << 24));
|
|
cfg = cfg & (~((1UL << 25) | (1UL << 22) | (1UL << 12)));
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
|
|
|
|
cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
|
|
cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
|
|
bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
|
|
|
|
/* Enable lmac */
|
|
bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
|
|
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
|
|
cfg &= ~SPU_CTL_LOW_POWER;
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
|
|
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
|
|
cfg &= ~SMU_TX_CTL_UNI_EN;
|
|
cfg |= SMU_TX_CTL_DIC_EN;
|
|
bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
|
|
|
|
/* take lmac_count into account */
|
|
bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
|
|
/* max packet size */
|
|
bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
bgx_xaui_check_link(struct lmac *lmac)
|
|
{
|
|
struct bgx *bgx = lmac->bgx;
|
|
int lmacid = lmac->lmacid;
|
|
int lmac_type = bgx->lmac_type;
|
|
uint64_t cfg;
|
|
|
|
bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
|
|
if (bgx->use_training) {
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
|
|
if ((cfg & (1UL << 13)) == 0) {
|
|
cfg = (1UL << 13) | (1UL << 14);
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
|
|
cfg |= (1UL << 0);
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
|
|
return (ENXIO);
|
|
}
|
|
}
|
|
|
|
/* wait for PCS to come out of reset */
|
|
if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1,
|
|
SPU_CTL_RESET, TRUE) != 0) {
|
|
device_printf(bgx->dev, "BGX SPU reset not completed\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
|
|
(lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
|
|
if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
|
|
SPU_BR_STATUS_BLK_LOCK, FALSE)) {
|
|
device_printf(bgx->dev,
|
|
"SPU_BR_STATUS_BLK_LOCK not completed\n");
|
|
return (ENXIO);
|
|
}
|
|
} else {
|
|
if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
|
|
SPU_BX_STATUS_RX_ALIGN, FALSE) != 0) {
|
|
device_printf(bgx->dev,
|
|
"SPU_BX_STATUS_RX_ALIGN not completed\n");
|
|
return (ENXIO);
|
|
}
|
|
}
|
|
|
|
/* Clear rcvflt bit (latching high) and read it back */
|
|
bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
|
|
if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
|
|
device_printf(bgx->dev, "Receive fault, retry training\n");
|
|
if (bgx->use_training) {
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
|
|
if ((cfg & (1UL << 13)) == 0) {
|
|
cfg = (1UL << 13) | (1UL << 14);
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
|
|
cfg = bgx_reg_read(bgx, lmacid,
|
|
BGX_SPUX_BR_PMD_CRTL);
|
|
cfg |= (1UL << 0);
|
|
bgx_reg_write(bgx, lmacid,
|
|
BGX_SPUX_BR_PMD_CRTL, cfg);
|
|
return (ENXIO);
|
|
}
|
|
}
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Wait for MAC RX to be ready */
|
|
if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_RX_CTL,
|
|
SMU_RX_CTL_STATUS, TRUE) != 0) {
|
|
device_printf(bgx->dev, "SMU RX link not okay\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Wait for BGX RX to be idle */
|
|
if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL,
|
|
SMU_CTL_RX_IDLE, FALSE) != 0) {
|
|
device_printf(bgx->dev, "SMU RX not idle\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Wait for BGX TX to be idle */
|
|
if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL,
|
|
SMU_CTL_TX_IDLE, FALSE) != 0) {
|
|
device_printf(bgx->dev, "SMU TX not idle\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
if ((bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) &
|
|
SPU_STATUS2_RCVFLT) != 0) {
|
|
device_printf(bgx->dev, "Receive fault\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Receive link is latching low. Force it high and verify it */
|
|
bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
|
|
if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_STATUS1,
|
|
SPU_STATUS1_RCV_LNK, FALSE) != 0) {
|
|
device_printf(bgx->dev, "SPU receive link down\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
|
|
cfg &= ~SPU_MISC_CTL_RX_DIS;
|
|
bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
bgx_poll_for_link(void *arg)
|
|
{
|
|
struct lmac *lmac;
|
|
uint64_t link;
|
|
|
|
lmac = (struct lmac *)arg;
|
|
|
|
/* Receive link is latching low. Force it high and verify it */
|
|
bgx_reg_modify(lmac->bgx, lmac->lmacid,
|
|
BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
|
|
bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
|
|
SPU_STATUS1_RCV_LNK, false);
|
|
|
|
link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
|
|
if (link & SPU_STATUS1_RCV_LNK) {
|
|
lmac->link_up = 1;
|
|
if (lmac->bgx->lmac_type == BGX_MODE_XLAUI)
|
|
lmac->last_speed = 40000;
|
|
else
|
|
lmac->last_speed = 10000;
|
|
lmac->last_duplex = 1;
|
|
} else {
|
|
lmac->link_up = 0;
|
|
}
|
|
|
|
if (lmac->last_link != lmac->link_up) {
|
|
lmac->last_link = lmac->link_up;
|
|
if (lmac->link_up)
|
|
bgx_xaui_check_link(lmac);
|
|
}
|
|
|
|
callout_reset(&lmac->check_link, hz * 2, bgx_poll_for_link, lmac);
|
|
}
|
|
|
|
static int
|
|
bgx_lmac_enable(struct bgx *bgx, uint8_t lmacid)
|
|
{
|
|
uint64_t __unused dmac_bcast = (1UL << 48) - 1;
|
|
struct lmac *lmac;
|
|
uint64_t cfg;
|
|
|
|
lmac = &bgx->lmac[lmacid];
|
|
lmac->bgx = bgx;
|
|
|
|
if (bgx->lmac_type == BGX_MODE_SGMII) {
|
|
lmac->is_sgmii = 1;
|
|
if (bgx_lmac_sgmii_init(bgx, lmacid) != 0)
|
|
return -1;
|
|
} else {
|
|
lmac->is_sgmii = 0;
|
|
if (bgx_lmac_xaui_init(bgx, lmacid, bgx->lmac_type))
|
|
return -1;
|
|
}
|
|
|
|
if (lmac->is_sgmii) {
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
|
|
cfg |= ((1UL << 2) | (1UL << 1)); /* FCS and PAD */
|
|
bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
|
|
bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
|
|
} else {
|
|
cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
|
|
cfg |= ((1UL << 2) | (1UL << 1)); /* FCS and PAD */
|
|
bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
|
|
bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
|
|
}
|
|
|
|
/* Enable lmac */
|
|
bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG,
|
|
CMR_EN | CMR_PKT_RX_EN | CMR_PKT_TX_EN);
|
|
|
|
/* Restore default cfg, incase low level firmware changed it */
|
|
bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
|
|
|
|
/* Add broadcast MAC into all LMAC's DMAC filters */
|
|
bgx_add_dmac_addr(dmac_bcast, 0, bgx->bgx_id, lmacid);
|
|
|
|
if ((bgx->lmac_type != BGX_MODE_XFI) &&
|
|
(bgx->lmac_type != BGX_MODE_XAUI) &&
|
|
(bgx->lmac_type != BGX_MODE_XLAUI) &&
|
|
(bgx->lmac_type != BGX_MODE_40G_KR) &&
|
|
(bgx->lmac_type != BGX_MODE_10G_KR)) {
|
|
if (lmac->phy_if_dev == NULL) {
|
|
device_printf(bgx->dev,
|
|
"LMAC%d missing interface to PHY\n", lmacid);
|
|
return (ENXIO);
|
|
}
|
|
|
|
if (LMAC_PHY_CONNECT(lmac->phy_if_dev, lmac->phyaddr,
|
|
lmacid) != 0) {
|
|
device_printf(bgx->dev,
|
|
"LMAC%d could not connect to PHY\n", lmacid);
|
|
return (ENXIO);
|
|
}
|
|
mtx_init(&lmac->check_link_mtx, "BGX link poll", NULL, MTX_DEF);
|
|
callout_init_mtx(&lmac->check_link, &lmac->check_link_mtx, 0);
|
|
mtx_lock(&lmac->check_link_mtx);
|
|
bgx_lmac_handler(lmac);
|
|
mtx_unlock(&lmac->check_link_mtx);
|
|
} else {
|
|
mtx_init(&lmac->check_link_mtx, "BGX link poll", NULL, MTX_DEF);
|
|
callout_init_mtx(&lmac->check_link, &lmac->check_link_mtx, 0);
|
|
mtx_lock(&lmac->check_link_mtx);
|
|
bgx_poll_for_link(lmac);
|
|
mtx_unlock(&lmac->check_link_mtx);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
bgx_lmac_disable(struct bgx *bgx, uint8_t lmacid)
|
|
{
|
|
struct lmac *lmac;
|
|
uint64_t cmrx_cfg;
|
|
|
|
lmac = &bgx->lmac[lmacid];
|
|
|
|
/* Stop callout */
|
|
callout_drain(&lmac->check_link);
|
|
mtx_destroy(&lmac->check_link_mtx);
|
|
|
|
cmrx_cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
|
|
cmrx_cfg &= ~(1 << 15);
|
|
bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cmrx_cfg);
|
|
bgx_flush_dmac_addrs(bgx, lmacid);
|
|
|
|
if ((bgx->lmac_type != BGX_MODE_XFI) &&
|
|
(bgx->lmac_type != BGX_MODE_XLAUI) &&
|
|
(bgx->lmac_type != BGX_MODE_40G_KR) &&
|
|
(bgx->lmac_type != BGX_MODE_10G_KR)) {
|
|
if (lmac->phy_if_dev == NULL) {
|
|
device_printf(bgx->dev,
|
|
"LMAC%d missing interface to PHY\n", lmacid);
|
|
return;
|
|
}
|
|
if (LMAC_PHY_DISCONNECT(lmac->phy_if_dev, lmac->phyaddr,
|
|
lmacid) != 0) {
|
|
device_printf(bgx->dev,
|
|
"LMAC%d could not disconnect PHY\n", lmacid);
|
|
return;
|
|
}
|
|
lmac->phy_if_dev = NULL;
|
|
}
|
|
}
|
|
|
|
static void
|
|
bgx_set_num_ports(struct bgx *bgx)
|
|
{
|
|
uint64_t lmac_count;
|
|
|
|
switch (bgx->qlm_mode) {
|
|
case QLM_MODE_SGMII:
|
|
bgx->lmac_count = 4;
|
|
bgx->lmac_type = BGX_MODE_SGMII;
|
|
bgx->lane_to_sds = 0;
|
|
break;
|
|
case QLM_MODE_XAUI_1X4:
|
|
bgx->lmac_count = 1;
|
|
bgx->lmac_type = BGX_MODE_XAUI;
|
|
bgx->lane_to_sds = 0xE4;
|
|
break;
|
|
case QLM_MODE_RXAUI_2X2:
|
|
bgx->lmac_count = 2;
|
|
bgx->lmac_type = BGX_MODE_RXAUI;
|
|
bgx->lane_to_sds = 0xE4;
|
|
break;
|
|
case QLM_MODE_XFI_4X1:
|
|
bgx->lmac_count = 4;
|
|
bgx->lmac_type = BGX_MODE_XFI;
|
|
bgx->lane_to_sds = 0;
|
|
break;
|
|
case QLM_MODE_XLAUI_1X4:
|
|
bgx->lmac_count = 1;
|
|
bgx->lmac_type = BGX_MODE_XLAUI;
|
|
bgx->lane_to_sds = 0xE4;
|
|
break;
|
|
case QLM_MODE_10G_KR_4X1:
|
|
bgx->lmac_count = 4;
|
|
bgx->lmac_type = BGX_MODE_10G_KR;
|
|
bgx->lane_to_sds = 0;
|
|
bgx->use_training = 1;
|
|
break;
|
|
case QLM_MODE_40G_KR4_1X4:
|
|
bgx->lmac_count = 1;
|
|
bgx->lmac_type = BGX_MODE_40G_KR;
|
|
bgx->lane_to_sds = 0xE4;
|
|
bgx->use_training = 1;
|
|
break;
|
|
default:
|
|
bgx->lmac_count = 0;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Check if low level firmware has programmed LMAC count
|
|
* based on board type, if yes consider that otherwise
|
|
* the default static values
|
|
*/
|
|
lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
|
|
if (lmac_count != 4)
|
|
bgx->lmac_count = lmac_count;
|
|
}
|
|
|
|
static void
|
|
bgx_init_hw(struct bgx *bgx)
|
|
{
|
|
int i;
|
|
|
|
bgx_set_num_ports(bgx);
|
|
|
|
bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
|
|
if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
|
|
device_printf(bgx->dev, "BGX%d BIST failed\n", bgx->bgx_id);
|
|
|
|
/* Set lmac type and lane2serdes mapping */
|
|
for (i = 0; i < bgx->lmac_count; i++) {
|
|
if (bgx->lmac_type == BGX_MODE_RXAUI) {
|
|
if (i)
|
|
bgx->lane_to_sds = 0x0e;
|
|
else
|
|
bgx->lane_to_sds = 0x04;
|
|
bgx_reg_write(bgx, i, BGX_CMRX_CFG,
|
|
(bgx->lmac_type << 8) | bgx->lane_to_sds);
|
|
continue;
|
|
}
|
|
bgx_reg_write(bgx, i, BGX_CMRX_CFG,
|
|
(bgx->lmac_type << 8) | (bgx->lane_to_sds + i));
|
|
bgx->lmac[i].lmacid_bd = lmac_count;
|
|
lmac_count++;
|
|
}
|
|
|
|
bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
|
|
bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
|
|
|
|
/* Set the backpressure AND mask */
|
|
for (i = 0; i < bgx->lmac_count; i++) {
|
|
bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
|
|
((1UL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
|
|
(i * MAX_BGX_CHANS_PER_LMAC));
|
|
}
|
|
|
|
/* Disable all MAC filtering */
|
|
for (i = 0; i < RX_DMAC_COUNT; i++)
|
|
bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
|
|
|
|
/* Disable MAC steering (NCSI traffic) */
|
|
for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
|
|
bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
|
|
}
|
|
|
|
static void
|
|
bgx_get_qlm_mode(struct bgx *bgx)
|
|
{
|
|
device_t dev = bgx->dev;
|
|
int lmac_type;
|
|
int train_en;
|
|
|
|
/* Read LMAC0 type to figure out QLM mode
|
|
* This is configured by low level firmware
|
|
*/
|
|
lmac_type = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
|
|
lmac_type = (lmac_type >> 8) & 0x07;
|
|
|
|
train_en = bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) &
|
|
SPU_PMD_CRTL_TRAIN_EN;
|
|
|
|
switch (lmac_type) {
|
|
case BGX_MODE_SGMII:
|
|
bgx->qlm_mode = QLM_MODE_SGMII;
|
|
if (bootverbose) {
|
|
device_printf(dev, "BGX%d QLM mode: SGMII\n",
|
|
bgx->bgx_id);
|
|
}
|
|
break;
|
|
case BGX_MODE_XAUI:
|
|
bgx->qlm_mode = QLM_MODE_XAUI_1X4;
|
|
if (bootverbose) {
|
|
device_printf(dev, "BGX%d QLM mode: XAUI\n",
|
|
bgx->bgx_id);
|
|
}
|
|
break;
|
|
case BGX_MODE_RXAUI:
|
|
bgx->qlm_mode = QLM_MODE_RXAUI_2X2;
|
|
if (bootverbose) {
|
|
device_printf(dev, "BGX%d QLM mode: RXAUI\n",
|
|
bgx->bgx_id);
|
|
}
|
|
break;
|
|
case BGX_MODE_XFI:
|
|
if (!train_en) {
|
|
bgx->qlm_mode = QLM_MODE_XFI_4X1;
|
|
if (bootverbose) {
|
|
device_printf(dev, "BGX%d QLM mode: XFI\n",
|
|
bgx->bgx_id);
|
|
}
|
|
} else {
|
|
bgx->qlm_mode = QLM_MODE_10G_KR_4X1;
|
|
if (bootverbose) {
|
|
device_printf(dev, "BGX%d QLM mode: 10G_KR\n",
|
|
bgx->bgx_id);
|
|
}
|
|
}
|
|
break;
|
|
case BGX_MODE_XLAUI:
|
|
if (!train_en) {
|
|
bgx->qlm_mode = QLM_MODE_XLAUI_1X4;
|
|
if (bootverbose) {
|
|
device_printf(dev, "BGX%d QLM mode: XLAUI\n",
|
|
bgx->bgx_id);
|
|
}
|
|
} else {
|
|
bgx->qlm_mode = QLM_MODE_40G_KR4_1X4;
|
|
if (bootverbose) {
|
|
device_printf(dev, "BGX%d QLM mode: 40G_KR4\n",
|
|
bgx->bgx_id);
|
|
}
|
|
}
|
|
break;
|
|
default:
|
|
bgx->qlm_mode = QLM_MODE_SGMII;
|
|
if (bootverbose) {
|
|
device_printf(dev, "BGX%d QLM default mode: SGMII\n",
|
|
bgx->bgx_id);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int
|
|
bgx_init_phy(struct bgx *bgx)
|
|
{
|
|
int err;
|
|
|
|
/* By default we fail */
|
|
err = ENXIO;
|
|
#ifdef FDT
|
|
err = bgx_fdt_init_phy(bgx);
|
|
#endif
|
|
#ifdef ACPI
|
|
if (err != 0) {
|
|
/* ARM64TODO: Add ACPI function here */
|
|
}
|
|
#endif
|
|
return (err);
|
|
}
|