372 lines
11 KiB
C
372 lines
11 KiB
C
/*-
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* Copyright (c) 2007 Bruce M. Simpson.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _SIBA_SIBAVAR_H_
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#define _SIBA_SIBAVAR_H_
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#include <sys/rman.h>
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struct siba_softc;
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struct siba_dev_softc;
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enum siba_device_ivars {
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SIBA_IVAR_VENDOR,
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SIBA_IVAR_DEVICE,
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SIBA_IVAR_REVID,
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SIBA_IVAR_CORE_INDEX
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};
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#define SIBA_ACCESSOR(var, ivar, type) \
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__BUS_ACCESSOR(siba, var, SIBA, ivar, type)
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SIBA_ACCESSOR(vendor, VENDOR, uint16_t)
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SIBA_ACCESSOR(device, DEVICE, uint16_t)
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SIBA_ACCESSOR(revid, REVID, uint8_t)
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SIBA_ACCESSOR(core_index, CORE_INDEX, uint8_t)
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#undef SIBA_ACCESSOR
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/* XXX just for SPROM1? */
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enum {
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SIBA_CCODE_WORLD,
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SIBA_CCODE_THAILAND,
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SIBA_CCODE_ISRAEL,
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SIBA_CCODE_JORDAN,
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SIBA_CCODE_CHINA,
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SIBA_CCODE_JAPAN,
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SIBA_CCODE_USA_CANADA_ANZ,
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SIBA_CCODE_EUROPE,
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SIBA_CCODE_USA_LOW,
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SIBA_CCODE_JAPAN_HIGH,
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SIBA_CCODE_ALL,
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SIBA_CCODE_NONE,
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};
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#define siba_mips_read_2(sc, core, reg) \
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bus_space_read_2((sc)->siba_mem_bt, (sc)->siba_mem_bh, \
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(core * SIBA_CORE_LEN) + (reg))
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#define siba_mips_read_4(sc, core, reg) \
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bus_space_read_4((sc)->siba_mem_bt, (sc)->siba_mem_bh, \
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(core * SIBA_CORE_LEN) + (reg))
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#define siba_mips_write_2(sc, core, reg, val) \
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bus_space_write_2((sc)->siba_mem_bt, (sc)->siba_mem_bh, \
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(core * SIBA_CORE_LEN) + (reg), (val))
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#define siba_mips_write_4(sc, core, reg, val) \
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bus_space_write_4((sc)->siba_mem_bt, (sc)->siba_mem_bh, \
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(core * SIBA_CORE_LEN) + (reg), (val))
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#define SIBA_READ_4(siba, reg) \
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bus_space_read_4((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg))
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#define SIBA_READ_2(siba, reg) \
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bus_space_read_2((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg))
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#define SIBA_READ_MULTI_1(siba, reg, addr, count) \
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bus_space_read_multi_1((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
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(reg), (addr), (count))
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#define SIBA_READ_MULTI_2(siba, reg, addr, count) \
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bus_space_read_multi_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
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(reg), (addr), (count))
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#define SIBA_READ_MULTI_4(siba, reg, addr, count) \
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bus_space_read_multi_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
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(reg), (addr), (count))
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#define SIBA_WRITE_4(siba, reg, val) \
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bus_space_write_4((siba)->siba_mem_bt, (siba)->siba_mem_bh, \
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(reg), (val))
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#define SIBA_WRITE_2(siba, reg, val) \
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bus_space_write_2((siba)->siba_mem_bt, (siba)->siba_mem_bh, \
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(reg), (val))
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#define SIBA_WRITE_MULTI_1(siba, reg, addr, count) \
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bus_space_write_multi_1((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
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(reg), (addr), (count))
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#define SIBA_WRITE_MULTI_2(siba, reg, addr, count) \
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bus_space_write_multi_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
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(reg), (addr), (count))
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#define SIBA_WRITE_MULTI_4(siba, reg, addr, count) \
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bus_space_write_multi_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,\
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(reg), (addr), (count))
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#define SIBA_BARRIER(siba, flags) \
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bus_space_barrier((siba)->siba_mem_bt, (siba)->siba_mem_bh, (0),\
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(0), (flags))
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#define SIBA_SETBITS_4(siba, reg, bits) \
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SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) | (bits))
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#define SIBA_SETBITS_2(siba, reg, bits) \
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SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) | (bits))
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#define SIBA_FILT_SETBITS_4(siba, reg, filt, bits) \
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SIBA_WRITE_4((siba), (reg), (SIBA_READ_4((siba), \
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(reg)) & (filt)) | (bits))
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#define SIBA_FILT_SETBITS_2(siba, reg, filt, bits) \
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SIBA_WRITE_2((siba), (reg), (SIBA_READ_2((siba), \
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(reg)) & (filt)) | (bits))
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#define SIBA_CLRBITS_4(siba, reg, bits) \
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SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) & ~(bits))
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#define SIBA_CLRBITS_2(siba, reg, bits) \
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SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) & ~(bits))
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#define SIBA_CC_READ32(scc, offset) \
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siba_read_4((scc)->scc_dev, offset)
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#define SIBA_CC_WRITE32(scc, offset, val) \
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siba_write_4((scc)->scc_dev, offset, val)
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#define SIBA_CC_MASK32(scc, offset, mask) \
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SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) & (mask))
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#define SIBA_CC_SET32(scc, offset, set) \
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SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) | (set))
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#define SIBA_CC_MASKSET32(scc, offset, mask, set) \
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SIBA_CC_WRITE32(scc, offset, \
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(SIBA_CC_READ32(scc, offset) & (mask)) | (set))
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enum siba_type {
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SIBA_TYPE_SSB,
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SIBA_TYPE_PCI,
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SIBA_TYPE_PCMCIA,
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};
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enum siba_clock {
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SIBA_CLOCK_DYNAMIC,
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SIBA_CLOCK_SLOW,
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SIBA_CLOCK_FAST,
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};
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enum siba_clksrc {
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SIBA_CC_CLKSRC_PCI,
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SIBA_CC_CLKSRC_CRYSTAL,
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SIBA_CC_CLKSRC_LOWPW,
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};
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struct siba_cc_pmu0_plltab {
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uint16_t freq; /* in kHz.*/
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uint8_t xf; /* crystal frequency */
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uint8_t wb_int;
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uint32_t wb_frac;
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};
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struct siba_cc_pmu1_plltab {
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uint16_t freq;
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uint8_t xf;
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uint8_t p1div;
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uint8_t p2div;
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uint8_t ndiv_int;
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uint32_t ndiv_frac;
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};
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struct siba_cc_pmu_res_updown {
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uint8_t res;
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uint16_t updown;
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};
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#define SIBA_CC_PMU_DEP_SET 1
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#define SIBA_CC_PMU_DEP_ADD 2
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#define SIBA_CC_PMU_DEP_REMOVE 3
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struct siba_cc_pmu_res_depend {
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uint8_t res;
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uint8_t task;
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uint32_t depend;
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};
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struct siba_sprom {
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uint8_t rev; /* revision */
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uint8_t mac_80211bg[6]; /* address for 802.11b/g */
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uint8_t mac_eth[6]; /* address for Ethernet */
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uint8_t mac_80211a[6]; /* address for 802.11a */
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uint8_t mii_eth0; /* MII address for eth0 */
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uint8_t mii_eth1; /* MII address for eth1 */
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uint8_t mdio_eth0; /* MDIO for eth0 */
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uint8_t mdio_eth1; /* MDIO for eth1 */
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uint8_t brev; /* board revision */
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uint8_t ccode; /* Country Code */
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uint8_t ant_a; /* A-PHY antenna */
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uint8_t ant_bg; /* B/G-PHY antenna */
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uint16_t pa0b0;
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uint16_t pa0b1;
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uint16_t pa0b2;
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uint16_t pa1b0;
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uint16_t pa1b1;
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uint16_t pa1b2;
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uint8_t gpio0;
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uint8_t gpio1;
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uint8_t gpio2;
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uint8_t gpio3;
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uint16_t maxpwr_a; /* A-PHY Max Power */
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uint16_t maxpwr_bg; /* BG-PHY Max Power */
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uint8_t tssi_a; /* Idle TSSI */
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uint8_t tssi_bg; /* Idle TSSI */
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uint16_t bf_lo; /* boardflags */
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uint16_t bf_hi; /* boardflags */
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struct {
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struct {
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int8_t a0, a1, a2, a3;
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} ghz24;
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struct {
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int8_t a0, a1, a2, a3;
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} ghz5;
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} again; /* antenna gain */
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};
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struct siba_cc_pmu {
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uint8_t rev; /* PMU rev */
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uint32_t freq; /* crystal freq in kHz */
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};
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struct siba_cc {
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struct siba_dev_softc *scc_dev;
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uint32_t scc_caps;
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struct siba_cc_pmu scc_pmu;
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uint16_t scc_powerup_delay;
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};
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struct siba_pci {
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struct siba_dev_softc *spc_dev;
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uint8_t spc_inited;
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uint8_t spc_hostmode;
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};
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struct siba_bus_ops {
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uint16_t (*read_2)(struct siba_dev_softc *,
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uint16_t);
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uint32_t (*read_4)(struct siba_dev_softc *,
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uint16_t);
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void (*write_2)(struct siba_dev_softc *,
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uint16_t, uint16_t);
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void (*write_4)(struct siba_dev_softc *,
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uint16_t, uint32_t);
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void (*read_multi_1)(struct siba_dev_softc *,
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void *, size_t, uint16_t);
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void (*read_multi_2)(struct siba_dev_softc *,
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void *, size_t, uint16_t);
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void (*read_multi_4)(struct siba_dev_softc *,
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void *, size_t, uint16_t);
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void (*write_multi_1)(struct siba_dev_softc *,
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const void *, size_t, uint16_t);
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void (*write_multi_2)(struct siba_dev_softc *,
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const void *, size_t, uint16_t);
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void (*write_multi_4)(struct siba_dev_softc *,
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const void *, size_t, uint16_t);
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};
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struct siba_dev_softc {
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struct siba_softc *sd_bus;
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struct siba_devid sd_id;
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const struct siba_bus_ops *sd_ops;
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uint8_t sd_coreidx;
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};
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struct siba_devinfo {
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struct resource_list sdi_rl;
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/*devhandle_t sdi_devhandle; XXX*/
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/*struct rman sdi_intr_rman;*/
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/* Accessors are needed for ivars below. */
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uint16_t sdi_vid;
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uint16_t sdi_devid;
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uint8_t sdi_rev;
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uint8_t sdi_idx; /* core index on bus */
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uint8_t sdi_irq; /* TODO */
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};
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struct siba_softc {
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/*
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* common variables which used for siba(4) bus and siba_bwn bridge.
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*/
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device_t siba_dev; /* Device ID */
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struct resource *siba_mem_res;
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bus_space_tag_t siba_mem_bt;
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bus_space_handle_t siba_mem_bh;
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bus_addr_t siba_maddr;
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bus_size_t siba_msize;
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uint8_t siba_ncores;
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/*
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* the following variables are only used for siba_bwn bridge.
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*/
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enum siba_type siba_type;
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int siba_invalid;
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struct siba_dev_softc *siba_curdev; /* only for PCI */
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struct siba_dev_softc siba_devs[SIBA_MAX_CORES];
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int siba_ndevs;
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uint16_t siba_pci_vid;
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uint16_t siba_pci_did;
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uint16_t siba_pci_subvid;
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uint16_t siba_pci_subdid;
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int siba_mem_rid;
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uint16_t siba_chipid; /* for CORE 0 */
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uint16_t siba_chiprev;
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uint8_t siba_chippkg;
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struct siba_cc siba_cc; /* ChipCommon */
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struct siba_pci siba_pci; /* PCI-core */
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const struct siba_bus_ops *siba_ops;
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/* board informations */
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uint16_t siba_board_vendor;
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uint16_t siba_board_type;
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uint16_t siba_board_rev;
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struct siba_sprom siba_sprom; /* SPROM */
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uint16_t siba_spromsize; /* in word size */
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};
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void siba_powerup(struct siba_softc *, int);
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uint16_t siba_read_2(struct siba_dev_softc *, uint16_t);
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void siba_write_2(struct siba_dev_softc *, uint16_t, uint16_t);
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uint32_t siba_read_4(struct siba_dev_softc *, uint16_t);
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void siba_write_4(struct siba_dev_softc *, uint16_t, uint32_t);
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void siba_dev_up(struct siba_dev_softc *, uint32_t);
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void siba_dev_down(struct siba_dev_softc *, uint32_t);
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int siba_powerdown(struct siba_softc *);
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int siba_dev_isup(struct siba_dev_softc *);
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void siba_pcicore_intr(struct siba_pci *, struct siba_dev_softc *);
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uint32_t siba_dma_translation(struct siba_dev_softc *);
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void *siba_dma_alloc_consistent(struct siba_dev_softc *, size_t,
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bus_addr_t *);
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void siba_read_multi_1(struct siba_dev_softc *, void *, size_t,
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uint16_t);
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void siba_read_multi_2(struct siba_dev_softc *, void *, size_t,
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uint16_t);
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void siba_read_multi_4(struct siba_dev_softc *, void *, size_t,
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uint16_t);
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void siba_write_multi_1(struct siba_dev_softc *, const void *,
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size_t, uint16_t);
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void siba_write_multi_2(struct siba_dev_softc *, const void *,
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size_t, uint16_t);
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void siba_write_multi_4(struct siba_dev_softc *, const void *,
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size_t, uint16_t);
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void siba_barrier(struct siba_dev_softc *, int);
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#endif /* _SIBA_SIBAVAR_H_ */
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