467 lines
14 KiB
C
467 lines
14 KiB
C
/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*-
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* Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* @(#)fpu.c 8.1 (Berkeley) 6/11/93
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* $NetBSD: fpu.c,v 1.11 2000/12/06 01:47:50 mrg Exp $
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include "namespace.h"
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#include <errno.h>
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#include <unistd.h>
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#include <signal.h>
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#include <stdlib.h>
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#include "un-namespace.h"
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#include "libc_private.h"
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#include <machine/fp.h>
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#include <machine/frame.h>
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#include <machine/fsr.h>
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#include <machine/instr.h>
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#include <machine/pcb.h>
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#include <machine/tstate.h>
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#include "__sparc_utrap_private.h"
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#include "fpu_emu.h"
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#include "fpu_extern.h"
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/*
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* Translate current exceptions into `first' exception. The
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* bits go the wrong way for ffs() (0x10 is most important, etc).
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* There are only 5, so do it the obvious way.
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*/
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#define X1(x) x
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#define X2(x) x,x
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#define X4(x) x,x,x,x
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#define X8(x) X4(x),X4(x)
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#define X16(x) X8(x),X8(x)
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static char cx_to_trapx[] = {
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X1(FSR_NX),
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X2(FSR_DZ),
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X4(FSR_UF),
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X8(FSR_OF),
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X16(FSR_NV)
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};
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#ifdef FPU_DEBUG
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#ifdef FPU_DEBUG_MASK
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int __fpe_debug = FPU_DEBUG_MASK;
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#else
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int __fpe_debug = 0;
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#endif
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#endif /* FPU_DEBUG */
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static int __fpu_execute(struct utrapframe *, struct fpemu *, u_int32_t, u_long);
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/*
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* Need to use an fpstate on the stack; we could switch, so we cannot safely
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* modify the pcb one, it might get overwritten.
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*/
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int
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__fpu_exception(struct utrapframe *uf)
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{
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struct fpemu fe;
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u_long fsr, tstate;
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u_int insn;
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int sig;
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fsr = uf->uf_fsr;
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switch (FSR_GET_FTT(fsr)) {
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case FSR_FTT_NONE:
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__utrap_write("lost FPU trap type\n");
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return (0);
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case FSR_FTT_IEEE:
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return (SIGFPE);
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case FSR_FTT_SEQERR:
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__utrap_write("FPU sequence error\n");
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return (SIGFPE);
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case FSR_FTT_HWERR:
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__utrap_write("FPU hardware error\n");
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return (SIGFPE);
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case FSR_FTT_UNFIN:
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case FSR_FTT_UNIMP:
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break;
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default:
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__utrap_write("unknown FPU error\n");
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return (SIGFPE);
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}
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fe.fe_fsr = fsr & ~FSR_FTT_MASK;
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insn = *(u_int32_t *)uf->uf_pc;
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if (IF_OP(insn) != IOP_MISC || (IF_F3_OP3(insn) != INS2_FPop1 &&
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IF_F3_OP3(insn) != INS2_FPop2))
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__utrap_panic("bogus FP fault");
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tstate = uf->uf_state;
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sig = __fpu_execute(uf, &fe, insn, tstate);
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if (sig != 0)
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return (sig);
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__asm __volatile("ldx %0, %%fsr" : : "m" (fe.fe_fsr));
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return (0);
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}
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#ifdef FPU_DEBUG
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/*
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* Dump a `fpn' structure.
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*/
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void
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__fpu_dumpfpn(struct fpn *fp)
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{
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static char *class[] = {
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"SNAN", "QNAN", "ZERO", "NUM", "INF"
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};
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printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2],
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fp->fp_sign ? '-' : ' ',
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fp->fp_mant[0], fp->fp_mant[1],
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fp->fp_mant[2], fp->fp_mant[3],
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fp->fp_exp);
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}
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#endif
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static int opmask[] = {0, 0, 1, 3};
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/* Decode 5 bit register field depending on the type. */
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#define RN_DECODE(tp, rn) \
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((tp == FTYPE_DBL || tp == FTYPE_EXT ? INSFPdq_RN((rn)) : (rn)) & \
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~opmask[tp])
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/* Operand size in 32-bit registers. */
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#define OPSZ(tp) ((tp) == FTYPE_LNG ? 2 : (1 << (tp)))
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/*
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* Helper for forming the below case statements. Build only the op3 and opf
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* field of the instruction, these are the only ones that need to match.
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*/
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#define FOP(op3, opf) \
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((op3) << IF_F3_OP3_SHIFT | (opf) << IF_F3_OPF_SHIFT)
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/*
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* Implement a move operation for all supported operand types. The additional
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* nand and xor parameters will be applied to the upper 32 bit word of the
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* source operand. This allows to implement fabs and fneg (for fp operands
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* only!) using this functions, too, by passing (1 << 31) for one of the
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* parameters, and 0 for the other.
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*/
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static void
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__fpu_mov(struct fpemu *fe, int type, int rd, int rs2, u_int32_t nand,
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u_int32_t xor)
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{
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u_int64_t tmp64;
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int i;
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if (type == FTYPE_INT || type == FTYPE_SNG)
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__fpu_setreg(rd, (__fpu_getreg(rs2) & ~nand) ^ xor);
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else {
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/*
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* Need to use the double versions to be able to access
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* the upper 32 fp registers.
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*/
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for (i = 0; i < OPSZ(type); i += 2, rd += 2, rs2 += 2) {
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tmp64 = __fpu_getreg64(rs2);
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if (i == 0)
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tmp64 = (tmp64 & ~((u_int64_t)nand << 32)) ^
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((u_int64_t)xor << 32);
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__fpu_setreg64(rd, tmp64);
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}
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}
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}
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static __inline void
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__fpu_ccmov(struct fpemu *fe, int type, int rd, int rs2,
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u_int32_t insn, int fcc)
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{
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if (IF_F4_COND(insn) == fcc)
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__fpu_mov(fe, type, rd, rs2, 0, 0);
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}
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static int
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__fpu_cmpck(struct fpemu *fe)
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{
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u_long fsr;
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int cx;
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/*
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* The only possible exception here is NV; catch it
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* early and get out, as there is no result register.
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*/
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cx = fe->fe_cx;
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fsr = fe->fe_fsr | (cx << FSR_CEXC_SHIFT);
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if (cx != 0) {
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if (fsr & (FSR_NV << FSR_TEM_SHIFT)) {
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fe->fe_fsr = (fsr & ~FSR_FTT_MASK) |
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FSR_FTT(FSR_FTT_IEEE);
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return (SIGFPE);
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}
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fsr |= FSR_NV << FSR_AEXC_SHIFT;
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}
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fe->fe_fsr = fsr;
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return (0);
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}
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/*
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* Execute an FPU instruction (one that runs entirely in the FPU; not
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* FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be
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* modified to reflect the setting the hardware would have left.
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*
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* Note that we do not catch all illegal opcodes, so you can, for instance,
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* multiply two integers this way.
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*/
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static int
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__fpu_execute(struct utrapframe *uf, struct fpemu *fe, u_int32_t insn, u_long tstate)
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{
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struct fpn *fp;
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int opf, rs1, rs2, rd, type, mask, cx, cond;
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u_long reg, fsr;
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u_int space[4];
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int i;
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/*
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* `Decode' and execute instruction. Start with no exceptions.
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* The type of any opf opcode is in the bottom two bits, so we
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* squish them out here.
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*/
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opf = insn & (IF_MASK(IF_F3_OP3_SHIFT, IF_F3_OP3_BITS) |
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IF_MASK(IF_F3_OPF_SHIFT + 2, IF_F3_OPF_BITS - 2));
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type = IF_F3_OPF(insn) & 3;
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rs1 = RN_DECODE(type, IF_F3_RS1(insn));
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rs2 = RN_DECODE(type, IF_F3_RS2(insn));
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rd = RN_DECODE(type, IF_F3_RD(insn));
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cond = 0;
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#ifdef notdef
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if ((rs1 | rs2 | rd) & opmask[type])
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return (SIGILL);
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#endif
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fsr = fe->fe_fsr;
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fe->fe_fsr &= ~FSR_CEXC_MASK;
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fe->fe_cx = 0;
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switch (opf) {
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case FOP(INS2_FPop2, INSFP2_FMOV_CC(IFCC_FCC(0))):
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__fpu_ccmov(fe, type, rd, rs2, insn, FSR_GET_FCC0(fsr));
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_CC(IFCC_FCC(1))):
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__fpu_ccmov(fe, type, rd, rs2, insn, FSR_GET_FCC1(fsr));
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_CC(IFCC_FCC(2))):
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__fpu_ccmov(fe, type, rd, rs2, insn, FSR_GET_FCC2(fsr));
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_CC(IFCC_FCC(3))):
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__fpu_ccmov(fe, type, rd, rs2, insn, FSR_GET_FCC3(fsr));
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_CC(IFCC_ICC)):
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__fpu_ccmov(fe, type, rd, rs2, insn,
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(tstate & TSTATE_ICC_MASK) >> TSTATE_ICC_SHIFT);
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_CC(IFCC_XCC)):
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__fpu_ccmov(fe, type, rd, rs2, insn,
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(tstate & TSTATE_XCC_MASK) >> (TSTATE_XCC_SHIFT));
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_RC(IRCOND_Z)):
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reg = __emul_fetch_reg(uf, IF_F4_RS1(insn));
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if (reg == 0)
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__fpu_mov(fe, type, rd, rs2, 0, 0);
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_RC(IRCOND_LEZ)):
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reg = __emul_fetch_reg(uf, IF_F4_RS1(insn));
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if (reg <= 0)
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__fpu_mov(fe, type, rd, rs2, 0, 0);
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_RC(IRCOND_LZ)):
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reg = __emul_fetch_reg(uf, IF_F4_RS1(insn));
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if (reg < 0)
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__fpu_mov(fe, type, rd, rs2, 0, 0);
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_RC(IRCOND_NZ)):
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reg = __emul_fetch_reg(uf, IF_F4_RS1(insn));
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if (reg != 0)
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__fpu_mov(fe, type, rd, rs2, 0, 0);
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_RC(IRCOND_GZ)):
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reg = __emul_fetch_reg(uf, IF_F4_RS1(insn));
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if (reg > 0)
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__fpu_mov(fe, type, rd, rs2, 0, 0);
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return (0);
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case FOP(INS2_FPop2, INSFP2_FMOV_RC(IRCOND_GEZ)):
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reg = __emul_fetch_reg(uf, IF_F4_RS1(insn));
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if (reg >= 0)
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__fpu_mov(fe, type, rd, rs2, 0, 0);
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return (0);
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case FOP(INS2_FPop2, INSFP2_FCMP):
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__fpu_explode(fe, &fe->fe_f1, type, rs1);
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__fpu_explode(fe, &fe->fe_f2, type, rs2);
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__fpu_compare(fe, 0, IF_F3_CC(insn));
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return (__fpu_cmpck(fe));
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case FOP(INS2_FPop2, INSFP2_FCMPE):
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__fpu_explode(fe, &fe->fe_f1, type, rs1);
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__fpu_explode(fe, &fe->fe_f2, type, rs2);
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__fpu_compare(fe, 1, IF_F3_CC(insn));
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return (__fpu_cmpck(fe));
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case FOP(INS2_FPop1, INSFP1_FMOV): /* these should all be pretty obvious */
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__fpu_mov(fe, type, rd, rs2, 0, 0);
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return (0);
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case FOP(INS2_FPop1, INSFP1_FNEG):
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__fpu_mov(fe, type, rd, rs2, 0, (1 << 31));
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return (0);
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case FOP(INS2_FPop1, INSFP1_FABS):
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__fpu_mov(fe, type, rd, rs2, (1 << 31), 0);
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return (0);
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case FOP(INS2_FPop1, INSFP1_FSQRT):
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__fpu_explode(fe, &fe->fe_f1, type, rs2);
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fp = __fpu_sqrt(fe);
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break;
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case FOP(INS2_FPop1, INSFP1_FADD):
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__fpu_explode(fe, &fe->fe_f1, type, rs1);
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__fpu_explode(fe, &fe->fe_f2, type, rs2);
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fp = __fpu_add(fe);
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break;
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case FOP(INS2_FPop1, INSFP1_FSUB):
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__fpu_explode(fe, &fe->fe_f1, type, rs1);
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__fpu_explode(fe, &fe->fe_f2, type, rs2);
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fp = __fpu_sub(fe);
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break;
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case FOP(INS2_FPop1, INSFP1_FMUL):
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__fpu_explode(fe, &fe->fe_f1, type, rs1);
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__fpu_explode(fe, &fe->fe_f2, type, rs2);
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fp = __fpu_mul(fe);
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break;
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case FOP(INS2_FPop1, INSFP1_FDIV):
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__fpu_explode(fe, &fe->fe_f1, type, rs1);
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__fpu_explode(fe, &fe->fe_f2, type, rs2);
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fp = __fpu_div(fe);
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break;
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case FOP(INS2_FPop1, INSFP1_FsMULd):
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case FOP(INS2_FPop1, INSFP1_FdMULq):
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if (type == FTYPE_EXT)
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return (SIGILL);
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__fpu_explode(fe, &fe->fe_f1, type, rs1);
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__fpu_explode(fe, &fe->fe_f2, type, rs2);
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type++; /* single to double, or double to quad */
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/*
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* Recalculate rd (the old type applied for the source regs
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* only, the target one has a different size).
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*/
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rd = RN_DECODE(type, IF_F3_RD(insn));
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fp = __fpu_mul(fe);
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break;
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case FOP(INS2_FPop1, INSFP1_FxTOs):
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case FOP(INS2_FPop1, INSFP1_FxTOd):
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case FOP(INS2_FPop1, INSFP1_FxTOq):
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type = FTYPE_LNG;
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__fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
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/* sneaky; depends on instruction encoding */
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type = (IF_F3_OPF(insn) >> 2) & 3;
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rd = RN_DECODE(type, IF_F3_RD(insn));
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break;
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case FOP(INS2_FPop1, INSFP1_FTOx):
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__fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
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type = FTYPE_LNG;
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mask = 1; /* needs 2 registers */
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rd = IF_F3_RD(insn) & ~mask;
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break;
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case FOP(INS2_FPop1, INSFP1_FTOs):
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case FOP(INS2_FPop1, INSFP1_FTOd):
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case FOP(INS2_FPop1, INSFP1_FTOq):
|
|
case FOP(INS2_FPop1, INSFP1_FTOi):
|
|
__fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
|
|
/* sneaky; depends on instruction encoding */
|
|
type = (IF_F3_OPF(insn) >> 2) & 3;
|
|
rd = RN_DECODE(type, IF_F3_RD(insn));
|
|
break;
|
|
default:
|
|
return (SIGILL);
|
|
}
|
|
|
|
/*
|
|
* ALU operation is complete. Collapse the result and then check
|
|
* for exceptions. If we got any, and they are enabled, do not
|
|
* alter the destination register, just stop with an exception.
|
|
* Otherwise set new current exceptions and accrue.
|
|
*/
|
|
__fpu_implode(fe, fp, type, space);
|
|
cx = fe->fe_cx;
|
|
if (cx != 0) {
|
|
mask = (fsr >> FSR_TEM_SHIFT) & FSR_TEM_MASK;
|
|
if (cx & mask) {
|
|
/* not accrued??? */
|
|
fsr = (fsr & ~FSR_FTT_MASK) |
|
|
FSR_FTT(FSR_FTT_IEEE) |
|
|
FSR_CEXC(cx_to_trapx[(cx & mask) - 1]);
|
|
return (SIGFPE);
|
|
}
|
|
fsr |= (cx << FSR_CEXC_SHIFT) | (cx << FSR_AEXC_SHIFT);
|
|
}
|
|
fe->fe_fsr = fsr;
|
|
if (type == FTYPE_INT || type == FTYPE_SNG)
|
|
__fpu_setreg(rd, space[0]);
|
|
else {
|
|
for (i = 0; i < OPSZ(type); i += 2) {
|
|
__fpu_setreg64(rd + i, ((u_int64_t)space[i] << 32) |
|
|
space[i + 1]);
|
|
}
|
|
}
|
|
return (0); /* success */
|
|
}
|