601a83560e
CPUs. The AR933x is a mips24k based SoC with an AR9380 series SoC on board, two gigabit ethernet interfaces and an internal 10/100mbit ethernet switch. There's also the normal interfaces (USB, ethernet, uart, GPIO.) The downside? There's a non-ns8250 UART device. With a very basic UART driver (not in this commit) the SoC is initialised and boots up. I'll commit the UART code soon and then link it into the general setup path. This code is a re-implementation based from the Linux kernel / openwrt AR933x support. TODO: * UART (obviously) * All of the ethernet, USB and wifi SoC glue, including ethernet PLL programming.
269 lines
6.1 KiB
C
269 lines
6.1 KiB
C
/*-
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* Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <net/ethernet.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/cpuregs.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <mips/atheros/ar71xxreg.h>
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#include <mips/atheros/ar933xreg.h>
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#include <mips/atheros/ar71xx_cpudef.h>
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#include <mips/atheros/ar71xx_setup.h>
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#include <mips/atheros/ar71xx_chip.h>
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#include <mips/atheros/ar933x_chip.h>
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static void
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ar933x_chip_detect_mem_size(void)
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{
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}
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static void
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ar933x_chip_detect_sys_frequency(void)
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{
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uint32_t clock_ctrl;
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uint32_t cpu_config;
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uint32_t freq;
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uint32_t t;
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t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP);
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if (t & AR933X_BOOTSTRAP_REF_CLK_40)
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u_ar71xx_refclk = (40 * 1000 * 1000);
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else
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u_ar71xx_refclk = (25 * 1000 * 1000);
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clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG);
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if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
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u_ar71xx_cpu_freq = u_ar71xx_refclk;
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u_ar71xx_ahb_freq = u_ar71xx_refclk;
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u_ar71xx_ddr_freq = u_ar71xx_refclk;
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} else {
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cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG);
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
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freq = u_ar71xx_refclk / t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
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AR933X_PLL_CPU_CONFIG_NINT_MASK;
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freq *= t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
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if (t == 0)
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t = 1;
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freq >>= t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
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u_ar71xx_cpu_freq = freq / t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
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u_ar71xx_ddr_freq = freq / t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
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u_ar71xx_ahb_freq = freq / t;
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}
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}
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static void
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ar933x_chip_device_stop(uint32_t mask)
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{
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uint32_t mask_inv, reg;
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mask_inv = mask;
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reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
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reg |= mask;
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reg &= ~mask_inv;
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ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg);
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}
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static void
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ar933x_chip_device_start(uint32_t mask)
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{
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uint32_t mask_inv, reg;
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mask_inv = mask;
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reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
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reg &= ~mask;
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reg |= mask_inv;
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ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg);
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}
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static int
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ar933x_chip_device_stopped(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
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return ((reg & mask) == mask);
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}
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static void
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ar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
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{
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/* XXX TODO */
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return;
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}
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/*
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* XXX TODO !!
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*/
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static void
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ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
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{
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switch (unit) {
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case 0:
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/* XXX TODO */
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break;
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case 1:
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/* XXX TODO */
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break;
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default:
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printf("%s: invalid PLL set for arge unit: %d\n",
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__func__, unit);
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return;
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}
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}
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static void
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ar933x_chip_ddr_flush_ge(int unit)
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{
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switch (unit) {
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case 0:
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
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break;
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case 1:
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
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break;
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default:
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printf("%s: invalid DDR flush for arge unit: %d\n",
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__func__, unit);
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return;
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}
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}
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static void
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ar933x_chip_ddr_flush_ip2(void)
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{
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
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}
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static uint32_t
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ar933x_chip_get_eth_pll(unsigned int mac, int speed)
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{
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return (0);
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}
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static void
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ar933x_chip_init_usb_peripheral(void)
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{
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#if 0
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7240:
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ar71xx_device_stop(AR724X_RESET_MODULE_USB_OHCI_DLL |
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AR724X_RESET_USB_HOST);
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DELAY(1000);
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ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL |
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AR724X_RESET_USB_HOST);
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DELAY(1000);
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/*
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* WAR for HW bug. Here it adjusts the duration
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* between two SOFS.
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*/
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ATH_WRITE_REG(AR71XX_USB_CTRL_FLADJ,
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(3 << USB_CTRL_FLADJ_A0_SHIFT));
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break;
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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ar71xx_device_start(AR724X_RESET_MODULE_USB_OHCI_DLL);
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DELAY(100);
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ar71xx_device_start(AR724X_RESET_USB_HOST);
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DELAY(100);
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ar71xx_device_start(AR724X_RESET_USB_PHY);
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DELAY(100);
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break;
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default:
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break;
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}
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#endif
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}
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struct ar71xx_cpu_def ar933x_chip_def = {
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&ar933x_chip_detect_mem_size,
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&ar933x_chip_detect_sys_frequency,
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&ar933x_chip_device_stop,
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&ar933x_chip_device_start,
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&ar933x_chip_device_stopped,
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&ar933x_chip_set_pll_ge,
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&ar933x_chip_set_mii_speed,
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&ar71xx_chip_set_mii_if,
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&ar933x_chip_ddr_flush_ge,
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&ar933x_chip_get_eth_pll,
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&ar933x_chip_ddr_flush_ip2,
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&ar933x_chip_init_usb_peripheral
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};
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