611f086953
In n32 and n64, add support for physical address above 4GB by having 64 bit page table entries and physical addresses. Major changes are: - param.h: update PTE sizes, masks and shift values to support 64 bit PTEs. - param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as ptoa), and reformat. - param.h: remove casting to unsigned long in trunc_page and round_page since this will be used on physical addresses. - _types.h: have 64 bit __vm_paddr_t for n32. - pte.h: update TLB LO0/1 access macros to support 64 bit PTE - pte.h: assembly macros for PTE operations. - proc.h: md_upte is now 64 bit for n32 and n64. - exception.S and swtch.S: use the new PTE macros for PTE operations. - cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64. - xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are supported now. Reviewed by: jmallett (earlier version)
82 lines
2.9 KiB
C
82 lines
2.9 KiB
C
/* $OpenBSD: proc.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)proc.h 8.1 (Berkeley) 6/10/93
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* JNPR: proc.h,v 1.7.2.1 2007/09/10 06:25:24 girish
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* $FreeBSD$
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*/
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#ifndef _MACHINE_PROC_H_
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#define _MACHINE_PROC_H_
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/*
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* Machine-dependent part of the proc structure.
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*/
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struct mdthread {
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int md_flags; /* machine-dependent flags */
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#if defined(__mips_n64) || defined(__mips_n32) /* PHYSADDR_64_BIT */
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uint64_t md_upte[KSTACK_PAGES]; /* ptes for mapping u pcb */
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#else
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int md_upte[KSTACK_PAGES];
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#endif
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int md_ss_addr; /* single step address for ptrace */
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int md_ss_instr; /* single step instruction for ptrace */
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register_t md_saved_intr;
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u_int md_spinlock_count;
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/* The following is CPU dependent, but kept in for compatibility */
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int md_pc_ctrl; /* performance counter control */
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int md_pc_count; /* performance counter */
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int md_pc_spill; /* performance counter spill */
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void *md_tls;
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};
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/* md_flags */
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#define MDTD_FPUSED 0x0001 /* Process used the FPU */
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struct mdproc {
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/* empty */
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};
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struct thread;
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void mips_cpu_switch(struct thread *, struct thread *, struct mtx *);
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void mips_cpu_throw(struct thread *, struct thread *);
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#ifdef __mips_n64
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#define KINFO_PROC_SIZE 1088
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#else
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#define KINFO_PROC_SIZE 816
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#endif
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#endif /* !_MACHINE_PROC_H_ */
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