6122f3e60d
branch. This brings us very close to the 3.0 release, which is expected in a week or two. MFC after: 1 week
144 lines
6.3 KiB
C++
144 lines
6.3 KiB
C++
//===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "DisassemblerEmitter.h"
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#include "CodeGenTarget.h"
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#include "X86DisassemblerTables.h"
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#include "X86RecognizableInstr.h"
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#include "ARMDecoderEmitter.h"
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#include "FixedLenDecoderEmitter.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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using namespace llvm;
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using namespace llvm::X86Disassembler;
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/// DisassemblerEmitter - Contains disassembler table emitters for various
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/// architectures.
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/// X86 Disassembler Emitter
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///
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/// *** IF YOU'RE HERE TO RESOLVE A "Primary decode conflict", LOOK DOWN NEAR
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/// THE END OF THIS COMMENT!
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///
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/// The X86 disassembler emitter is part of the X86 Disassembler, which is
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/// documented in lib/Target/X86/X86Disassembler.h.
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///
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/// The emitter produces the tables that the disassembler uses to translate
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/// instructions. The emitter generates the following tables:
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///
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/// - One table (CONTEXTS_SYM) that contains a mapping of attribute masks to
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/// instruction contexts. Although for each attribute there are cases where
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/// that attribute determines decoding, in the majority of cases decoding is
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/// the same whether or not an attribute is present. For example, a 64-bit
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/// instruction with an OPSIZE prefix and an XS prefix decodes the same way in
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/// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix
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/// may have effects on its execution, but does not change the instruction
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/// returned.) This allows considerable space savings in other tables.
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/// - Six tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM,
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/// THREEBYTEA6_SYM, and THREEBYTEA7_SYM contain the hierarchy that the
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/// decoder traverses while decoding an instruction. At the lowest level of
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/// this hierarchy are instruction UIDs, 16-bit integers that can be used to
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/// uniquely identify the instruction and correspond exactly to its position
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/// in the list of CodeGenInstructions for the target.
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/// - One table (INSTRUCTIONS_SYM) contains information about the operands of
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/// each instruction and how to decode them.
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///
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/// During table generation, there may be conflicts between instructions that
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/// occupy the same space in the decode tables. These conflicts are resolved as
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/// follows in setTableFields() (X86DisassemblerTables.cpp)
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///
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/// - If the current context is the native context for one of the instructions
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/// (that is, the attributes specified for it in the LLVM tables specify
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/// precisely the current context), then it has priority.
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/// - If the current context isn't native for either of the instructions, then
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/// the higher-priority context wins (that is, the one that is more specific).
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/// That hierarchy is determined by outranks() (X86DisassemblerTables.cpp)
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/// - If the current context is native for both instructions, then the table
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/// emitter reports a conflict and dies.
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///
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/// *** RESOLUTION FOR "Primary decode conflict"S
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///
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/// If two instructions collide, typically the solution is (in order of
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/// likelihood):
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///
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/// (1) to filter out one of the instructions by editing filter()
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/// (X86RecognizableInstr.cpp). This is the most common resolution, but
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/// check the Intel manuals first to make sure that (2) and (3) are not the
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/// problem.
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/// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are
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/// accurate. Sometimes they are not.
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/// (3) to fix the tables to reflect the actual context (for example, required
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/// prefixes), and possibly to add a new context by editing
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/// lib/Target/X86/X86DisassemblerDecoderCommon.h. This is unlikely to be
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/// the cause.
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///
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/// DisassemblerEmitter.cpp contains the implementation for the emitter,
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/// which simply pulls out instructions from the CodeGenTarget and pushes them
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/// into X86DisassemblerTables.
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/// X86DisassemblerTables.h contains the interface for the instruction tables,
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/// which manage and emit the structures discussed above.
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/// X86DisassemblerTables.cpp contains the implementation for the instruction
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/// tables.
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/// X86ModRMFilters.h contains filters that can be used to determine which
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/// ModR/M values are valid for a particular instruction. These are used to
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/// populate ModRMDecisions.
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/// X86RecognizableInstr.h contains the interface for a single instruction,
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/// which knows how to translate itself from a CodeGenInstruction and provide
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/// the information necessary for integration into the tables.
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/// X86RecognizableInstr.cpp contains the implementation for a single
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/// instruction.
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void DisassemblerEmitter::run(raw_ostream &OS) {
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CodeGenTarget Target(Records);
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OS << "/*===- TableGen'erated file "
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<< "---------------------------------------*- C -*-===*\n"
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<< " *\n"
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<< " * " << Target.getName() << " Disassembler\n"
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<< " *\n"
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<< " * Automatically generated file, do not edit!\n"
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<< " *\n"
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<< " *===---------------------------------------------------------------"
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<< "-------===*/\n";
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// X86 uses a custom disassembler.
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if (Target.getName() == "X86") {
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DisassemblerTables Tables;
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const std::vector<const CodeGenInstruction*> &numberedInstructions =
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Target.getInstructionsByEnumValue();
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for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i)
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RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i);
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// FIXME: As long as we are using exceptions, might as well drop this to the
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// actual conflict site.
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if (Tables.hasConflicts())
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throw TGError(Target.getTargetRecord()->getLoc(),
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"Primary decode conflict");
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Tables.emit(OS);
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return;
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}
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// ARM and Thumb have a CHECK() macro to deal with DecodeStatuses.
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if (Target.getName() == "ARM" ||
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Target.getName() == "Thumb") {
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FixedLenDecoderEmitter(Records,
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"ARM",
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"if (!Check(S, ", ")) return MCDisassembler::Fail;",
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"S", "MCDisassembler::Fail",
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" MCDisassembler::DecodeStatus S = MCDisassembler::Success;\n(void)S;").run(OS);
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return;
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}
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FixedLenDecoderEmitter(Records, Target.getName()).run(OS);
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}
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