310 lines
10 KiB
C++
310 lines
10 KiB
C++
//===---------------------- ProcessImplicitDefs.cpp -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "processimplicitdefs"
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#include "llvm/CodeGen/ProcessImplicitDefs.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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char ProcessImplicitDefs::ID = 0;
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static RegisterPass<ProcessImplicitDefs> X("processimpdefs",
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"Process Implicit Definitions.");
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void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addPreserved<AliasAnalysis>();
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AU.addPreserved<LiveVariables>();
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AU.addRequired<LiveVariables>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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AU.addPreservedID(TwoAddressInstructionPassID);
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AU.addPreservedID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool
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ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI,
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unsigned Reg, unsigned OpIdx,
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const TargetInstrInfo *tii_,
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SmallSet<unsigned, 8> &ImpDefRegs) {
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unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
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if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
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Reg == SrcReg &&
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(DstSubReg == 0 || ImpDefRegs.count(DstReg)))
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return true;
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switch(OpIdx) {
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case 1:
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return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 ||
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ImpDefRegs.count(MI->getOperand(0).getReg()));
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case 2:
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return MI->isSubregToReg() && (MI->getOperand(0).getSubReg() == 0 ||
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ImpDefRegs.count(MI->getOperand(0).getReg()));
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default: return false;
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}
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}
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static bool isUndefCopy(MachineInstr *MI, unsigned Reg,
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const TargetInstrInfo *tii_,
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SmallSet<unsigned, 8> &ImpDefRegs) {
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if (MI->isCopy()) {
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MachineOperand &MO0 = MI->getOperand(0);
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MachineOperand &MO1 = MI->getOperand(1);
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if (MO1.getReg() != Reg)
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return false;
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if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg()))
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return true;
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return false;
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}
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unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
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if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
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if (Reg != SrcReg)
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return false;
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if (DstSubReg == 0 || ImpDefRegs.count(DstReg))
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return true;
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}
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return false;
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}
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/// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure
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/// there is one implicit_def for each use. Add isUndef marker to
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/// implicit_def defs and their uses.
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bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
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<< "********** Function: "
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<< ((Value*)fn.getFunction())->getName() << '\n');
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bool Changed = false;
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const TargetInstrInfo *tii_ = fn.getTarget().getInstrInfo();
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const TargetRegisterInfo *tri_ = fn.getTarget().getRegisterInfo();
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MachineRegisterInfo *mri_ = &fn.getRegInfo();
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LiveVariables *lv_ = &getAnalysis<LiveVariables>();
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SmallSet<unsigned, 8> ImpDefRegs;
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SmallVector<MachineInstr*, 8> ImpDefMIs;
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SmallVector<MachineInstr*, 4> RUses;
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SmallPtrSet<MachineBasicBlock*,16> Visited;
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SmallPtrSet<MachineInstr*, 8> ModInsts;
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MachineBasicBlock *Entry = fn.begin();
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for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
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DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
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DFI != E; ++DFI) {
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MachineBasicBlock *MBB = *DFI;
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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I != E; ) {
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MachineInstr *MI = &*I;
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++I;
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if (MI->isImplicitDef()) {
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if (MI->getOperand(0).getSubReg())
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continue;
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unsigned Reg = MI->getOperand(0).getReg();
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ImpDefRegs.insert(Reg);
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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for (const unsigned *SS = tri_->getSubRegisters(Reg); *SS; ++SS)
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ImpDefRegs.insert(*SS);
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}
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ImpDefMIs.push_back(MI);
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continue;
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}
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// Eliminate %reg1032:sub<def> = COPY undef.
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if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
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MachineOperand &MO = MI->getOperand(1);
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if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) {
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if (MO.isKill()) {
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LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
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vi.removeKill(MI);
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}
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MI->eraseFromParent();
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Changed = true;
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continue;
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}
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}
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bool ChangedToImpDef = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = MI->getOperand(i);
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if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (!ImpDefRegs.count(Reg))
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continue;
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// Use is a copy, just turn it into an implicit_def.
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if (CanTurnIntoImplicitDef(MI, Reg, i, tii_, ImpDefRegs)) {
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bool isKill = MO.isKill();
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MI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF));
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for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
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MI->RemoveOperand(j);
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if (isKill) {
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ImpDefRegs.erase(Reg);
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LiveVariables::VarInfo& vi = lv_->getVarInfo(Reg);
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vi.removeKill(MI);
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}
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ChangedToImpDef = true;
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Changed = true;
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break;
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}
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Changed = true;
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MO.setIsUndef();
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// This is a partial register redef of an implicit def.
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// Make sure the whole register is defined by the instruction.
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if (MO.isDef()) {
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MI->addRegisterDefined(Reg);
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continue;
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}
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if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
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// Make sure other uses of
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for (unsigned j = i+1; j != e; ++j) {
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MachineOperand &MOJ = MI->getOperand(j);
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if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg)
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MOJ.setIsUndef();
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}
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ImpDefRegs.erase(Reg);
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}
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}
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if (ChangedToImpDef) {
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// Backtrack to process this new implicit_def.
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--I;
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} else {
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for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
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MachineOperand& MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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ImpDefRegs.erase(MO.getReg());
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}
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}
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}
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// Any outstanding liveout implicit_def's?
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for (unsigned i = 0, e = ImpDefMIs.size(); i != e; ++i) {
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MachineInstr *MI = ImpDefMIs[i];
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unsigned Reg = MI->getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
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!ImpDefRegs.count(Reg)) {
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// Delete all "local" implicit_def's. That include those which define
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// physical registers since they cannot be liveout.
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MI->eraseFromParent();
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Changed = true;
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continue;
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}
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// If there are multiple defs of the same register and at least one
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// is not an implicit_def, do not insert implicit_def's before the
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// uses.
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bool Skip = false;
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SmallVector<MachineInstr*, 4> DeadImpDefs;
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for (MachineRegisterInfo::def_iterator DI = mri_->def_begin(Reg),
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DE = mri_->def_end(); DI != DE; ++DI) {
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MachineInstr *DeadImpDef = &*DI;
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if (!DeadImpDef->isImplicitDef()) {
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Skip = true;
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break;
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}
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DeadImpDefs.push_back(DeadImpDef);
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}
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if (Skip)
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continue;
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// The only implicit_def which we want to keep are those that are live
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// out of its block.
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for (unsigned j = 0, ee = DeadImpDefs.size(); j != ee; ++j)
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DeadImpDefs[j]->eraseFromParent();
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Changed = true;
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// Process each use instruction once.
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for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
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UE = mri_->use_end(); UI != UE; ++UI) {
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if (UI.getOperand().isUndef())
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continue;
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MachineInstr *RMI = &*UI;
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if (ModInsts.insert(RMI))
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RUses.push_back(RMI);
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}
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for (unsigned i = 0, e = RUses.size(); i != e; ++i) {
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MachineInstr *RMI = RUses[i];
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// Turn a copy use into an implicit_def.
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if (isUndefCopy(RMI, Reg, tii_, ImpDefRegs)) {
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RMI->setDesc(tii_->get(TargetOpcode::IMPLICIT_DEF));
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bool isKill = false;
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SmallVector<unsigned, 4> Ops;
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for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
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MachineOperand &RRMO = RMI->getOperand(j);
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if (RRMO.isReg() && RRMO.getReg() == Reg) {
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Ops.push_back(j);
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if (RRMO.isKill())
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isKill = true;
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}
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}
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// Leave the other operands along.
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for (unsigned j = 0, ee = Ops.size(); j != ee; ++j) {
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unsigned OpIdx = Ops[j];
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RMI->RemoveOperand(OpIdx-j);
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}
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// Update LiveVariables varinfo if the instruction is a kill.
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if (isKill) {
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LiveVariables::VarInfo& vi = lv_->getVarInfo(Reg);
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vi.removeKill(RMI);
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}
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continue;
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}
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// Replace Reg with a new vreg that's marked implicit.
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const TargetRegisterClass* RC = mri_->getRegClass(Reg);
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unsigned NewVReg = mri_->createVirtualRegister(RC);
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bool isKill = true;
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for (unsigned j = 0, ee = RMI->getNumOperands(); j != ee; ++j) {
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MachineOperand &RRMO = RMI->getOperand(j);
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if (RRMO.isReg() && RRMO.getReg() == Reg) {
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RRMO.setReg(NewVReg);
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RRMO.setIsUndef();
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if (isKill) {
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// Only the first operand of NewVReg is marked kill.
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RRMO.setIsKill();
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isKill = false;
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}
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}
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}
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}
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RUses.clear();
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ModInsts.clear();
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}
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ImpDefRegs.clear();
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ImpDefMIs.clear();
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}
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return Changed;
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}
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